3D cell and array structures
Various 3D cells, array structures, and processes are disclosed. In an embodiment, a memory cell array structure is provided that includes memory cells organized into rows and columns, input lines where each input line is connected to memory cells in a selected row, and the input lines form input line groups, and output lines where each output line is connected to memory cells in a selected column, and the output lines form output line groups. The array structure also includes a multiplexer having multiplexer inputs and multiplexer outputs such that the multiplexer inputs are connected to the output line groups, neuron circuits connected to the multiplexer outputs, and the memory cell array simulates a neural network in which the input lines simulate input layer neurons of the neural network, and the output lines simulate output layer neurons of the neural network.
1 . A memory cell array structure, comprising:
a plurality of memory cells organized into a plurality of rows and columns, wherein each memory cell is configured to generate a cell current based on a received input signal and stored data;
a plurality of input lines, wherein each input line is connected to memory cells in a selected row, and wherein the plurality of input lines form a plurality of input line groups;
a plurality of output lines, wherein each output line is connected to memory cells in a selected column, and wherein the plurality of output lines form a plurality of output line groups;
a selector configured to sequentially select the input line groups to limit a number of selected memory cells per output line in an output line group;
a multiplexer having multiplexer inputs and multiplexer outputs, wherein the multiplexer inputs are connected to the output line groups, wherein the multiplexer is configured to sequentially select which of the output line groups are connected to the multiplexer outputs;
neuron circuits connected to the multiplexer outputs, wherein the neuron circuits are configured to convert a summation of cell currents in a selected output line group into digital data; and
wherein the memory cell array simulates a neural network in which the plurality of input lines simulate input layer neurons of the neural network, and the plurality of output lines simulate output layer neurons of the neural network.
2 . The memory cell array structure of claim 1 , wherein the plurality of memory cells comprise one of floating body cells, flash memory cells, resistive random-access memory cells, ferroelectric random-access memory cells, magneto-resistive random-access memory cells, phase-change memory cells, and mem-transistor cells.
3 . The memory cell array structure of claim 1 , where the neuron circuits comprise at least one of an analog-to-digital converter, operational amplifier, or a comparator to convert the summation of cell currents into digital data.
4 . The memory cell array structure of claim 3 , where the analog-to-digital converter, operational amplifier, or comparator circuits also perform an ‘activation function’.
5 . The memory cell array structure of claim 1 , wherein the multiplexer sequentially selects the output line groups and passes the summation of the cell currents to the neuron circuits.
6 . A 3D cell structure, comprising:
a plurality of blocks, wherein each block comprises an input buffer, an array comprising memory cells configured to generate a cell current based on a received input signal and stored data, and a neuron circuit, and wherein each neuron circuit outputs an output data group by converting a summation of cell currents into digital data;
a plurality of data buffers having buffer inputs and buffer outputs, wherein the plurality of buffer inputs are configured to receive the output data groups from the plurality of neuron circuits, respectively, and wherein the plurality of data buffers are configured to sequentially load the output data groups;
a plurality of activation circuits having circuit inputs and circuit outputs, wherein the plurality of circuit inputs are connected to the plurality of buffer outputs, respectively, and wherein the plurality of circuit outputs are configured to output activation results; and
wherein the 3D cell structure simulates a neural network in which the plurality of input buffers simulate input neuron groups of the neural network, the plurality of data buffers simulate output neuron groups of the neural network, and the plurality of activation circuits simulate activation functions of the neural network.
7 . The 3D cell structure of claim 6 , wherein the memory cells comprise one of floating body cells, flash memory cells, resistive random-access memory cells, ferroelectric random-access memory cells, magneto-resistive random-access memory cells, phase-change memory cells, and mem-transistor cells.
8 . The 3D cell structure of claim 6 , wherein the neuron circuit comprises at least one of an analog-to-digital converter, operational amplifier, or a comparator to convert the summation of cell currents from the memory cells into the digital data.
9 . The 3D cell structure of claim 8 , wherein the analog-to-digital converter, operational amplifier, or comparator also perform an activation function.
10 . The 3D cell structure of claim 6 , wherein the array in each block is divided into a plurality of sub-arrays to reduce signal delay, and wherein the input buffer applies input data groups to selected input lines in the sub-arrays.
11 . The 3D cell structure of claim 6 , further comprising multiplexers connected to output line groups in the array, wherein the multiplexers sequentially select the output line groups and pass the summation of the cell currents to the neuron circuit.
12 . The memory cell array structure of claim 1 , wherein the memory cells are configured to provide negative weights for synapses of the neural network using differential pairs of memory cells connected to the input lines and output lines.
13 . The memory cell array structure of claim 1 , wherein the memory cell array is divided into a plurality of sub-arrays to reduce signal delay, and wherein the input line groups apply input data to selected sub-arrays sequentially.
14 . The memory cell array structure of claim 1 , wherein the neuron circuits are configured to support analog neural networks by processing multi-level cell currents or digital neural networks by processing binary threshold levels.