Layout for imaging system and pixel cell array with quad row select transistors
A pixel cell array includes a plurality of pixel cells, each including one or more photodiodes configured to generate image charge in response to incident light, a floating diffusion coupled to receive the image charge, a source-follower transistor having a gate coupled to the floating diffusion to generate an image signal at a first source/drain region of the source-follower transistor in response to the image charge in the floating diffusion, a first row select transistor having a first source/drain region coupled to the first source/drain region of the source-follower transistor, and a second row select transistor having a first source/drain region coupled to a second source/drain region of the first row select transistor. The first source/drain regions of the second row select transistors included in a first pixel cell and a second pixel cell included in the plurality of pixel cells are coupled together through a common junction.
1 . A pixel cell array disposed in or on a semiconductor material, comprising:
a plurality of pixel cells arranged into rows and columns including a first pixel cell and a second pixel cell adjacent to the first pixel cell, wherein each pixel cell included in the plurality of pixel cells includes:
one or more photodiodes configured to generate image charge in response to incident light;
a floating diffusion coupled to receive the image charge generated by the one or more photodiodes;
a source-follower transistor having a gate coupled to the floating diffusion to generate an image signal at a first source/drain region of the source-follower transistor in response to the image charge in the floating diffusion;
a first row select transistor having a first source/drain region coupled to the first source/drain region of the source-follower transistor to output the image signal; and
a second row select transistor having a first source/drain region coupled to a second source/drain region of the first row select transistor, and
a common junction disposed in the semiconductor material, wherein the first source/drain regions of the second row select transistors included in the first and the second pixel cells are coupled together through the common junction.
2 . The pixel cell array of claim 1 , wherein the first source/drain region of the second row select transistor is coupled to the second source/drain region of the first row select transistor through the common junction for the first and the second pixel cells.
3 . The pixel cell array of claim 1 , wherein the first and the second row select transistors included in the first and the second pixel cells are coupled together without metal wiring.
4 . The pixel cell array of claim 1 , further comprising a transistor region disposed between the one or more photodiodes of the first pixel cell and the one or more photodiodes of the second pixel cell, and wherein the common junction is disposed within the transistor region.
5 . The pixel cell array of claim 4 , wherein a cross-section of the pixel cell array along a direction parallel to a column direction extends through the transistor region, the common junction, the gates of the source-follower transistors included in the first and the second pixel cells, and gates of the first row select transistors included in the first and the second pixel cells.
6 . The pixel cell array of claim 1 , wherein the gate of the first row select transistor included in the first pixel cell and the gate of the first row select transistor included in the second pixel cell are disposed between the gate of the source-follower transistor included in the first pixel cell and the gate of the source-follower transistor included in the second pixel cell.
7 . The pixel cell array of claim 1 , wherein a gate of the first row select transistor included in the first pixel cell is disposed between a pair of photodiodes included in one or more photodiodes of the first pixel cell, and wherein a gate of the first row select transistor included in the second pixel cell is disposed between a pair of photodiodes included in the one or more photodiodes of the second pixel cell, and wherein the common junction is disposed between the gate of the first row select transistor included in the first pixel cell and the gate of the second row select transistor included in the second pixel cell.
8 . The pixel cell array of claim 1 , wherein the floating diffusion of the first pixel cell is a split floating diffusion including a first portion and a second portion physically separated from the first portion, wherein the first portion and the second portion are formed in the semiconductor material, wherein the first portion is disposed between a first pair of photodiodes included in the one or more photodiodes of the first pixel cell and the gate of the source-follower transistor of the first pixel cell, wherein the second portion is disposed between a second pair of photodiodes included in the one or more photodiodes of the first pixel cell and the gate of the source-follower transistor of the first pixel cell.
9 . The pixel cell array of claim 1 , wherein the plurality of pixel cells is organized into pairs of adjacent pixel cells, each including respective instances of the first pixel cell and the second pixel cell.
10 . The pixel cell array of claim 9 , wherein a first one of the pairs of adjacent pixel cells is horizontally adjacent to a second one of the pairs of adjacent pixel cells, and wherein gates of the second row select transistors of the first and the second pixel cells included in the first one of the pairs of adjacent pixel cells and the second one of the pairs of adjacent pixel cells are aligned.
11 . The pixel cell array of claim 9 , further comprising an interconnect coupling the second row select transistors of a first one of the pairs of adjacent pixel cells to a closest one of the second row select transistors included in a second one of the pairs of adjacent pixel cells.
12 . The pixel cell array of claim 9 , wherein a first one of the pairs of adjacent pixel cells is vertically adjacent to a third one of the pairs of adjacent pixel cells, and wherein gates of the first row select transistors of the first and the second pixel cells included in the first one of the pairs of adjacent pixel cells and the third one of the pairs of adjacent pixel cells are aligned.
13 . The pixel cell array of claim 9 , wherein the pairs of adjacent pixel cells includes a first one, a second one, a third one, and a fourth one to form 2×2 pixel cell unit structures, wherein the first one is horizontally adjacent to the second one and vertically adjacent to the third one, wherein the fourth one is horizontally adjacent to the third one and vertically adjacent to the second one.
14 . The pixel cell array of claim 13 , wherein the first pixel cell of the first one of the pairs of adjacent pixel cells is horizontally adjacent to the first pixel cell of the second one of the pairs of adjacent pixel cell, wherein the first pixel cell of the third one of the pairs of adjacent pixel cells is horizontally adjacent to the first pixel cell of the fourth one of the pairs of adjacent pixel cells,
wherein the pixel cell array further comprises a first interconnect coupling the second row select transistor included in the second pixel cell of the first one of the pairs of adjacent pixel cells with the second row select transistor of the second pixel cell included in second one of the pairs of adjacent pixel cells.
15 . The pixel cell array of claim 14 , wherein the common junction is associated with the first one of the pairs of adjacent pixel cells, and wherein the first interconnect extends over the common junction.
16 . The pixel cell array of claim 14 , wherein the pixel cell array further comprises a second interconnect coupling the second row select transistors included in the first pixel cell and the second pixel cell of the fourth one of the pairs of adjacent pixel cells with the second row select transistor of the second pixel cell included in third one of the pairs of adjacent pixel cells.
17 . The pixel cell array of claim 9 , wherein each of the pairs of adjacent pixel cells includes a corresponding instance of the common junction.
18 . An imaging system, comprising:
a pixel cell array disposed in or on a semiconductor material, the pixel cell array including a plurality of pixel cells arranged into rows and columns, the plurality of pixel cells including a first pixel cell and a second pixel cell adjacent to the first pixel cell, and wherein each pixel cell included in the plurality of pixel cells includes:
one or more photodiodes;
a floating diffusion coupled to the one or more photodiodes;
a source-follower transistor having a gate coupled to the floating diffusion;
a first row select transistor and a second row select transistor, wherein the first row select transistor is coupled between the source-follower transistor and the second row select transistor;
a common junction coupled between a gate of the first row select transistor included in the first pixel cell and a gate of the first row select transistor of the second pixel cell, wherein the common junction is further coupled between a gate of the second row select transistor included in the first pixel cell and a gate of the second row select transistor included in the second pixel cell.
19 . The imaging system of claim 18 , further comprising a plurality of column bitlines including a first column bitline, wherein the gate of the second row select transistor included in the first pixel cell is disposed between the common junction and a source/drain region of the second row select transistor included in the first pixel cell, wherein the gate of the second row select transistor included in the second pixel cell is disposed between the common junction and a source/drain region of the second row select transistor included in the second pixel cell, and wherein the source/drain regions of the second row select transistor included in the first pixel cell and the second pixel cell are coupled to the first column bitline.
20 . The imaging system of claim 18 , further comprising a plurality of column bitlines including a first column bitline and a second column bitline adjacent to the first column bitline, wherein the plurality of pixel cells are organized into pairs of adjacent pixel cells, each including respective instances of the first pixel cell and the second pixel cell with the first pixel cell vertically adjacent to the second pixel cell, wherein a first one of the pairs of adjacent pixel cells is horizontally adjacent to a second one of the pairs of adjacent pixel cells,
wherein source/drain regions of the second row select transistors included in the first and the second pixel cells of the first one of the pairs of adjacent pixel cells are coupled to the first column bitline,
wherein a source/drain region of the second row select transistor included in the first pixel cell of the second one of the pairs of adjacent pixel cells is coupled to the first column bitline, and
wherein a source/drain region of the second row select transistor included in the first pixel cell of the second one of the pairs of adjacent pixel cells is coupled to the second column bitline.