Semiconductor device comprising a connecting layer including an array of connecting pads and a capacitive structure
View Patent ↗A semiconductor device includes a substrate, a connecting layer on the substrate, and a capacitor structure arranged on the connecting layer. The connecting layer includes an array of connecting pads, a peripheral structure adjacent to the array of connecting pads, and a plurality of first extending pads arranged between the peripheral structure and the array of connecting pads. The connecting pads respectively have one of the bottom electrodes of the capacitor structure disposed thereon. The first extending pads respectively have two of the bottom electrodes of the capacitor structure disposed thereon to reinforce the peripheral portions of the capacitor structure.
1 . A semiconductor device, comprising:
a substrate;
a connecting layer on the substrate and comprising:
an array of connecting pads comprising a plurality of connecting pads arranged along a first direction and a second direction and separated from each other;
a peripheral structure comprising a first edge and a second edge adjacent to two adjacent sides of the array of connecting pads; and
a plurality of first extending pads arranged between the first edge of the peripheral structure and the array of connecting pads; and
a capacitor structure comprising a plurality of bottom electrodes disposed on the connecting layer, wherein the connecting pads respectively have one of the bottom electrodes disposed thereon, the first extending pads respectively have at least two of the bottom electrodes disposed thereon.
2 . The semiconductor device according to claim 1 , wherein the first edge and the second edge of the peripheral structure extend along different directions and are connected by a third edge of the peripheral structure, wherein the semiconductor device further comprises:
a third extending pad arranged between the third edge and the array of connecting pads; and
a plurality of fourth extending pads arranged between the second edge and the array of connecting pads, wherein along the first direction, lengths of the first extending pads are larger than a length of the third extending pad, and the length of the third extending pad is larger than lengths of the fourth extending pads.
3 . The semiconductor device according to claim 2 , wherein the fourth extending pads alternately have one of the bottom electrodes disposed thereon.
4 . The semiconductor device according to claim 2 , further comprising:
a fifth extending pad arranged between one of the first extending pads and the third extending pad and physically connected to the third edge, wherein along the first direction, a length of the fifth extending pad is larger than the length of the third extending pad and smaller than the lengths of the first extending pads.
5 . The semiconductor device according to claim 4 , wherein the fifth extending pad has one of the bottom electrodes disposed thereon.
6 . The semiconductor device according to claim 1 , further comprising:
a plurality of second extending pads arranged alternately with the first extending pads and between the first edge of the peripheral structure and the array of connecting pads, wherein the second extending pads respectively have one of the bottom electrodes disposed thereon.
7 . The semiconductor device according to claim 6 , wherein along the first direction, lengths of the first extending pads are larger than lengths of the second extending pads.
8 . The semiconductor device according to claim 6 , wherein the second extending pads are physically connected to the first edge of the peripheral structure, the first extending pads are physically separated from the first edge of the peripheral structure by a dielectric layer.
9 . The semiconductor device according to claim 6 , wherein the first edge and the second edge of the peripheral structure extend along different directions and are connected by a third edge of the peripheral structure, wherein the semiconductor device further comprises:
a third extending pad arranged between the third edge and the array of connecting pads; and
a plurality of fourth extending pads arranged between the second edge and the array of connecting pads, wherein along the first direction, lengths of the second extending pads are larger than a length of the third extending pad, and the length of the third extending pad is larger than lengths of the fourth extending pads.
10 . The semiconductor device according to claim 9 , further comprising:
a fifth extending pad arranged between one of the first extending pads and the third extending pad and physically connected to the third edge, wherein along the first direction, a length of the fifth extending pad is larger than the length of the third extending pad and smaller than the lengths of the second extending pads.
11 . The semiconductor device according to claim 1 , wherein the first edge of the peripheral structure has a straight profile, the second edge has a wave profile.
12 . A semiconductor device, comprising:
a substrate;
a connecting layer on the substrate and comprising:
an array of connecting pads comprising a plurality of connecting pads arranged along a first direction and a second direction;
a peripheral structure comprising a first edge and a second edge adjacent to two adjacent sides of the array of connecting pads; and
a plurality of first extending pads and second extending pads alternately arranged between the first edge of the peripheral structure and the array of connecting pads, wherein along the first direction, lengths of the first extending pads are larger than lengths of the second extending pads; and
a capacitor structure comprising a plurality of bottom electrodes disposed on the connecting layer, wherein the connecting pads respectively have one of the bottom electrodes disposed thereon, the first extending pads respectively have a number N+1 of the bottom electrodes disposed thereon, wherein the number N is an integer number of 0, 1, or 2, the second extending pads respectively have the number N of the bottom electrodes disposed thereon.
13 . The semiconductor device according to claim 12 , wherein the second extending pads are physically connected to the first edge of the peripheral structure, the first extending pads are physically separated from the first edge of the peripheral structure by a dielectric layer.
14 . The semiconductor device according to claim 12 , wherein the first edge of the peripheral structure has a straight profile, the second edge has a wave profile.
15 . The semiconductor device according to claim 12 , wherein the first edge and the second edge of the peripheral structure extend along different directions and are connected by a third edge of the peripheral structure, wherein the semiconductor device further comprises:
a third extending pad arranged between the third edge and the array of connecting pads; and
a plurality of fourth extending pads arranged between the second edge and the array of connecting pads, wherein along the first direction, lengths of the first extending pads are larger than a length of the third extending pad, and the length of the third extending pad is larger than lengths of the fourth extending pads.
16 . The semiconductor device according to claim 15 , wherein the lengths of the second extending pads are larger than the length of the third extending pad.
17 . The semiconductor device according to claim 15 , wherein the fourth extending pads alternately have one of the bottom electrodes disposed thereon.
18 . The semiconductor device according to claim 15 , further comprising:
a fifth extending pad arranged between one of the first extending pads and the third extending pad and physically connected to the third edge, wherein along the first direction, a length of the fifth extending pad is larger than the length of the third extending pad and smaller than the lengths of the second extending pads.
19 . The semiconductor device according to claim 18 , wherein the fifth extending pad has the number N of the bottom electrodes disposed thereon.