Semiconductor structure and method for manufacturing the same
A semiconductor device includes a first channel region disposed in a first device region over a substrate; a first gate dielectric layer disposed over the first channel region; a second gate dielectric layer disposed over the second channel region; and a gate electrode disposed over the first gate dielectric layer. The first gate dielectric layer includes a first dipole dopant and the second gate dielectric layer includes a second dipole dopant embedded therein. A boundary between the first gate dielectric layer and the second gate dielectric layer contains the first dipole dopant and the second dipole dopant.
1 . A method comprising:
forming a gate dielectric over a first channel region and a second channel region;
forming a first dipole dopant layer and a blocking layer over the gate dielectric over the first channel region, the first dipole dopant layer being between the blocking layer and the first channel region, the second channel region being free of the first dipole dopant layer and the blocking layer, the first dipole dopant layer comprising first dipole dopants;
forming a second dipole dopant layer over the blocking layer over the first channel region and over the gate dielectric over the second channel region, the second dipole dopant layer comprising second dipole dopants;
performing an anneal to simultaneously drive the first dipole dopants from the first dipole dopant layer into the gate dielectric over the first channel region to form a first doped gate dielectric layer and drive the second dipole dopants from the second dipole dopant layer into the gate dielectric over the second channel region to form a second doped gate dielectric layer, wherein the blocking layer blocks the second dipole dopants from the gate dielectric over the first channel region;
removing remaining portions of the first dipole dopant layer, the second dipole dopant layer, and the blocking layer from over the first channel region and the second channel region; and
forming a first gate electrode over the first doped gate dielectric layer and a second gate electrode over the second doped gate dielectric layer.
2 . The method of claim 1 , wherein the first dipole dopants and the second dipole dopants have a same conductivity type, wherein the first dipole dopant layer is a different material than the second dipole dopant layer.
3 . The method of claim 1 , wherein the first dipole dopants diffuse through a partial thickness of the gate dielectric over the first channel region during the anneal.
4 . The method of claim 1 , wherein the first dipole dopants diffuse completely through the gate dielectric and partially into an interfacial layer underlying the gate dielectric during the anneal.
5 . The method of claim 1 , wherein the first doped gate dielectric layer has an average atomic concentration of the first dipole dopants between about 1E12 atoms/cm 2 and about 1E15 atoms/cm 2 .
6 . The method of claim 1 , wherein the blocking layer comprises aluminum oxide, silicon oxide, silicon oxycarbide, silicon nitride, silicon oxycarbonitride, silicon carbide, or titanium nitride.
7 . The method of claim 1 , wherein the first dipole dopants have an opposite conductivity type from the second dipole dopants.
8 . The method of claim 7 , wherein the first gate electrode and the second gate electrode comprise a same conductive material and are portions of a continuous gate electrode structure.
9 . The method of claim 8 , wherein performing the anneal forms a boundary gate dielectric region between the first doped gate dielectric layer and the second doped gate dielectric layer, wherein the boundary gate dielectric region is doped with the first dipole dopants and the second dipole dopants.
10 . A method comprising:
forming a gate dielectric over a first channel region and a second channel region, the gate dielectric extending continuously from over the first channel region to over the second channel region;
forming a first dipole dopant layer and a blocking layer over the first channel region, the first dipole dopant layer being between the blocking layer and the first channel region, the second channel region being free of the first dipole dopant layer and the blocking layer, the first dipole dopant layer comprising first dipole dopants;
forming a second dipole dopant layer over the blocking layer over the first channel region and over the gate dielectric over the second channel region, the second dipole dopant layer comprising second dipole dopants;
performing an anneal to drive the first dipole dopants from the first dipole dopant layer into the gate dielectric over the first channel region to form a first doped gate dielectric layer and drive the second dipole dopants from the second dipole dopant layer into the gate dielectric over the second channel region to form a second doped gate dielectric layer, wherein the blocking layer blocks the second dipole dopants from the gate dielectric over the first channel region, wherein performing the anneal forms a boundary gate dielectric region between the first doped gate dielectric layer and the second doped gate dielectric layer, wherein the boundary gate dielectric region is doped with the first dipole dopants and the second dipole dopants;
removing remaining portions of the first dipole dopant layer, the second dipole dopant layer, and the blocking layer from over the first channel region and the second channel region; and
forming a gate electrode over the first doped gate dielectric layer and the second doped gate dielectric layer.
11 . The method of claim 10 , wherein the boundary gate dielectric region has a width between about 1 angstrom and about 10 angstroms.
12 . The method of claim 10 , wherein a lateral distance between the boundary gate dielectric region and the first channel region is between about 5 nm and about 100 nm.
13 . The method of claim 10 , wherein a ratio of a width of the boundary gate dielectric region to a lateral distance between the boundary gate dielectric region and the first channel region is between about 1:5 and about 1:50.
14 . The method of claim 10 , wherein the first dipole dopant layer and the second dipole dopant layer comprise different materials having a same conductivity type.
15 . The method of claim 10 , wherein the first dipole dopant layer and the second dipole dopant layer comprise different materials having opposite conductivity types.
16 . A method comprising:
forming a first gate region over a first channel region, the first gate region including a first gate electrode over a first portion of a gate dielectric layer, wherein the first portion of the gate dielectric layer is doped with a first dopant; and
forming a second gate region over a second channel region, the second gate region including a second gate electrode over a second portion of the gate dielectric layer, wherein the second portion of the gate dielectric layer is doped with a second dopant different than the first dopant, wherein a first threshold voltage of the first gate region is different from a second threshold voltage of the second gate region, wherein the gate dielectric layer includes a boundary region between the first gate region and the second gate region, wherein the boundary region includes the first dopant and the second dopant, wherein the gate dielectric layer in the boundary region is contiguous with the gate dielectric layer in the first gate region and the gate dielectric layer in the second gate region.
17 . The method of claim 16 , wherein the first dopant has an opposite conductivity type from the second dopant.
18 . The method of claim 16 , further comprising forming an interfacial layer underlying the gate dielectric layer.
19 . The method of claim 16 , wherein a portion of the gate dielectric layer in the first gate region is free of the first dopant.
20 . The method of claim 18 , wherein the first dopant extends through the gate dielectric layer and partially into the interfacial layer in the first gate region.