Pixel with dual-PD layout
Various embodiments of the present disclosure are directed towards an image sensor comprising a pixel with a dual-PD layout for enhanced scaling down. The pixel spans a first integrated circuit (IC) die and a second IC die stacked with the first IC die. The pixel comprises a plurality of photodetectors in the first IC die, and further comprises a plurality of pixel transistors split amongst the first IC die and the second IC die. The plurality of photodetectors are grouped into one or more pairs, each having the dual-PD layout. A DTI structure completely and individually surrounds the plurality of photodetectors, and further extends completely through a substrate within which the plurality of photodetectors are arranged. As such, the DTI structure completely separates the plurality of photodetectors from each other.
1 . A method for forming an image sensor, comprising:
forming a first integrated circuit (IC) die, comprising:
forming a plurality of photodetectors in a first substrate;
forming a plurality of first pixel transistors on the first substrate, individual to and respectively bordering the plurality of photodetectors, wherein the plurality of photodetectors and the plurality of first pixel transistors form a first pixel portion; and
forming an interconnect structure overlying the plurality of first pixel transistors and electrically coupling individual source/drain regions of the plurality of first pixel transistors together;
forming a second IC die, comprising:
forming a plurality of second pixel transistors on a second substrate, wherein the second pixel transistors form a second pixel portion;
bonding the first IC die and the second IC die together such that the first pixel portion and the second pixel portion are stacked and electrically coupled together to form a pixel; and
forming a deep trench isolation (DTI) structure extending through the first substrate and separating the plurality of photodetectors from each other after the bonding.
2 . The method according to claim 1 , wherein the bonding comprises bonding conductors respectively of the first and second IC dies together at an interface and bonding dielectric layers respectively of the first and second IC dies together at the interface.
3 . The method according to claim 1 , further comprising:
forming a third IC die, comprising:
forming a plurality of logic devices on a third substrate; and
forming an interconnect structure overlying and electrically coupled to the logic devices, wherein the logic devices and the interconnect structure form an application-specific integrated circuit (ASIC); and
bonding the second IC die and the third IC die together, such that the second IC die is between the first IC die and the third IC die and such that the ASIC is electrically coupled to the pixel.
4 . The method according to claim 1 , wherein the forming of the DTI structure comprises forming a metal core lined by a dielectric liner.
5 . The method according to claim 1 , further comprising:
forming a micro lens overlying the plurality of photodetectors on an opposite side of the first substrate as the second IC die.
6 . The method according to claim 1 , wherein the interconnect structure comprises a conductive wire and a plurality of conductive vias extending from the conductive wire respectively to the individual source/drain regions of the plurality of first pixel transistors.
7 . The method according to claim 6 , wherein the conductive wire has a ring-shaped top geometry.
8 . A method for forming an image sensor, comprising:
forming a first semiconductor structure, which comprises a pair of photodetectors in a first substrate;
forming a second semiconductor structure, which comprises a plurality of pixel transistors on a second substrate;
bonding the first semiconductor structure and the second semiconductor structure together, such that the pair of photodetectors and the plurality of pixel transistors form a pixel;
forming a trench isolation structure extending completely through the first substrate and completely separating the pair of photodetectors from each other; and
forming a color filter shared by and overlying both of the pair of photodetectors on an opposite side of the first substrate as the second semiconductor structure.
9 . The method according to claim 8 , wherein the method further comprises:
performing a first planarization into the second substrate after the bonding and before the forming of the trench isolation structure to reduce a thickness of the second substrate.
10 . The method according to claim 9 , wherein the method further comprises:
performing a second planarization into the first substrate after the first planarization and before the forming of the trench isolation structure to reduce a thickness of the first substrate.
11 . The method according to claim 8 , wherein the first semiconductor structure further comprises a pair of transfer transistors that further form the pixel and that are individual to and respectively border the pair of photodetectors, wherein the pair of photodetectors comprise individual collector regions buried in the first substrate and having a same doping type as individual source/drain regions of the pair of transfer transistors, and wherein the method further comprises:
performing a planarization into the first substrate before the forming of the trench isolation structure to expose the pair of collector regions.
12 . The method according to claim 8 , wherein the pair of photodetectors comprise a first photodetector and a second photodetector that are formed bordering each other and having individual top profiles stepping down towards a width-wise center between the first and second photodetectors, and wherein the trench isolation structure is formed extending completely through the first substrate at the width-wise center.
13 . The method according to claim 8 , wherein the first semiconductor structure further comprises a pair of transfer transistors further forming the pixel and individual to and respectively bordering the pair of photodetectors, and wherein the forming of the first semiconductor structure comprises forming a ring-shaped conductive wire overlying and electrically coupled to individual source/drain regions of the pair of transfer transistors.
14 . The method according to claim 13 , wherein the first semiconductor structure further comprises an additional pair of photodetectors in the first substrate and an additional pair of transfer transistors, wherein the additional pair of photodetectors and the additional pair of transfer transistors further form the pixel, and wherein the forming of the first semiconductor structure further comprises forming an additional ring-shaped conductive wire overlying and electrically coupled to individual source/drain regions of the additional pair of transfer transistors.
15 . A method for forming an image sensor, comprising:
forming a first integrated circuit (IC) die comprising a plurality of photodetectors and a plurality of transfer transistors, wherein the plurality of photodetectors and source/drain regions of the plurality of transfer transistors are in a first substrate;
forming a second IC die comprising a plurality of pixel transistors on a second substrate;
bonding the second IC die to the first substrate to form a pixel that comprises the plurality of photodetectors, the plurality of transfer transistors, and the plurality of pixel transistors;
forming a third IC die comprising a plurality of logic transistors;
bonding the third IC die to the second IC die on an opposite side of the second IC die as the first IC die; and
forming a trench isolation structure extending through the first substrate after the bonding of the third IC die, wherein the trench isolation structure separates the source/drain regions of the plurality of transfer transistors from each other.
16 . The method according to claim 15 , wherein the first IC die repeats across a first wafer, the second IC die repeats across a second wafer, and the third IC die repeats across a third wafer, and wherein the bonding of the second IC die and the bonding of the third IC die correspond to wafer-to-wafer bonding.
17 . The method according to claim 16 , further comprising:
dicing the first, second, and third wafers to separate the first, second, and third IC dies from remainders of the first, second, and third wafers.
18 . The method according to claim 16 , further comprising:
performing a first trimming process to remove edge portions of the second wafer, such that a width of the second wafer is less than a width of the first wafer, wherein the first trimming process is performed before the bonding of the third IC die; and
performing a second trimming process to remove edge portions of the first wafer, such that a width of the first wafer is less than a width of the third wafer, wherein the second trimming process is performed before the forming of the trench isolation structure.
19 . The method according to claim 15 , wherein the plurality of photodetectors comprise individual collector regions formed buried in the first substrate, and wherein the plurality of transfer transistors are formed respectively overlying the individual collector regions and having individual source/drain regions with a same doping type as the individual collector regions.
20 . The method according to claim 19 , wherein the individual source/drain regions are formed respectively overlying the individual collector regions.