Integrated circuit packages and methods of forming the same
An integrated circuit package includes an interposer, the interposer including: a first redistribution layer, a second redistribution layer over the first redistribution layer in a central region of the interposer, a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view, a third redistribution layer over the second redistribution layer and the dielectric layer, and a first direct via extending through the dielectric layer. A conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via.
1 . An integrated circuit package comprising:
an interposer comprising:
a first redistribution layer;
a second redistribution layer over the first redistribution layer in a central region of the interposer;
a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view;
a third redistribution layer over the second redistribution layer and the dielectric layer; and
a first direct via embedded in the dielectric layer, wherein the first direct via is spaced apart from the second redistribution layer by the dielectric layer, wherein the dielectric layer contacts and extends along sidewalls of the first direct via, wherein a conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via; and
an integrated circuit die over the third redistribution layer of the interposer, wherein the integrated circuit die is coupled to the conductive feature of the first redistribution layer through the first direct via.
2 . The integrated circuit package of claim 1 , further comprising a second direct via through the dielectric layer, wherein the second direct via has a greater height than the first direct via.
3 . The integrated circuit package of claim 1 , further comprising a second direct via through the dielectric layer, wherein the first direct via and the second direct via are on opposite sides of the central region of the interposer.
4 . The integrated circuit package of claim 1 , further comprising a package substrate attached to the interposer, wherein the package substrate comprises a substrate core and a first routing structure at a first side of the substrate core, wherein the first routing structure comprises first dielectric layers and first conductive features embedded in the first dielectric layers, wherein the first routing structure comprises a first spiral routing stack in a peripheral region of the package substrate, wherein the first spiral routing stack comprises:
a first conductive trace embedded in a first dielectric layer of the first dielectric layers, wherein the first conductive trace has a first semicircular shape or a first semi-polygonal shape in the top-down view;
a second conductive trace embedded in a second dielectric layer of the first dielectric layers, wherein the second dielectric layer is over the first dielectric layer, wherein the second conductive trace has a second semicircular shape or a second semi-polygonal shape in the top-down view; and
a via embedded in the second dielectric layer and connecting the first conductive trace to the second conductive trace, wherein in the top-down view, the first conductive trace and the second conductive trace form a circular shape or a polygonal shape.
5 . An integrated circuit package comprising:
a package substrate comprising:
a substrate core, the substrate core having a first side and a second side opposite the first side;
a first through via extending through the substrate core;
a first routing structure on the first side of the substrate core, wherein the first routing structure comprises first dielectric layers and first conductive features embedded in the first dielectric layers, wherein the first routing structure comprising comprises a first spiral routing stack, wherein the first spiral routing stack comprises:
a first conductive trace embedded in a first dielectric layer of the first dielectric layers, wherein the first conductive trace has a first semicircular shape or a first semi-polygonal shape in a top view;
a second conductive trace embedded in a second dielectric layer of the first dielectric layers, wherein the second dielectric layer is over the first dielectric layer, wherein the second conductive trace has a second semicircular shape or a second semi-polygonal shape in the top view; and
a via embedded in the second dielectric layer and connecting the first conductive trace to the second conductive trace, wherein in the top view, the first conductive trace and the second conductive trace form a circular shape or a polygonal shape; and
a second routing structure on the second side of the substrate core, the second routing structure comprising a second spiral routing stack, the second spiral routing stack being coupled to the first spiral routing stack through the first through via; and
a first package component attached to the first routing structure of the package substrate.
6 . The integrated circuit package of claim 5 , wherein the first package component comprises a first interposer coupled to the first routing structure and a first integrated circuit die coupled to the first interposer.
7 . The integrated circuit package of claim 6 , wherein the first interposer is an organic interposer.
8 . The integrated circuit package of claim 6 , wherein the first interposer is a silicon interposer.
9 . The integrated circuit package of claim 6 , wherein the first interposer comprises:
a first redistribution layer;
a second redistribution layer over the first redistribution layer;
a dielectric layer over the first redistribution layer, the dielectric layer extending around the second redistribution layer in the top view;
a third redistribution layer over the second redistribution layer and the dielectric layer; and
a direct via extending through the dielectric layer, wherein the direct via is embedded in the dielectric layer and is separated from the second redistribution layer by the dielectric layer, wherein a conductive feature of the third redistribution layer is electrically coupled to a conductive feature of the first redistribution layer through the direct via.
10 . The integrated circuit package of claim 6 , further comprising:
a second package component attached to the first routing structure of the package substrate,
wherein the first routing structure further comprises a third spiral routing stack, the third spiral routing stack being disposed between the first package component and the second package component in the top view.
11 . The integrated circuit package of claim 6 , further comprising a surface-mounted device on the first routing structure, the surface-mounted device being coupled to the first spiral routing stack.
12 . An integrated circuit package comprising:
an interposer comprising:
a first redistribution structure;
a second redistribution structure over the first redistribution structure;
a first dielectric layer surrounding the second redistribution structure in a top-down view;
a third redistribution structure over the second redistribution structure and the first dielectric layer; and
a first conductive via extending through the first dielectric layer, wherein the first conductive via is separated from the second redistribution structure by the first dielectric layer, wherein the first conductive via electrically couples the third redistribution structure and the first redistribution structure; and
a package substrate underneath the interposer, the package substrate comprising:
a substrate core;
a first routing structure on a first side of the substrate core, wherein the first routing structure is electrically coupled to the interposer; and
a second routing structure on a second side of the substrate core.
13 . The integrated circuit package of claim 12 , wherein the first dielectric layer is a single layer of a homogeneous composition.
14 . The integrated circuit package of claim 12 , wherein the first conductive via is in contact with the first redistribution structure and the third redistribution structure.
15 . The integrated circuit package of claim 12 , wherein a top surface of the first conductive via is coplanar with a top surface of the first dielectric layer.
16 . The integrated circuit package of claim 12 , further comprising an integrated circuit die over the interposer, wherein the integrated circuit die is electrically coupled to the third redistribution structure, and wherein the integrated circuit die overlaps the first conductive via.
17 . The integrated circuit package of claim 12 , wherein the package substrate further comprises a second conductive via extending through the substrate core, wherein the second conductive via electrically couples the first routing structure and the second routing structure.
18 . The integrated circuit package of claim 17 , wherein the first routing structure comprises a first spiral routing stack, wherein the first spiral routing stack comprises a first conductive trace having a first semicircular shape or a first semi-polygonal shape, wherein the first spiral routing stack has a first inductance, and wherein the first spiral routing stack is electrically coupled to the second conductive via.
19 . The integrated circuit package of claim 18 , wherein the second routing structure comprises a second spiral routing stack, wherein the second spiral routing stack comprises a second conductive trace having a second semicircular shape or a second semi-polygonal shape, wherein the second spiral routing stack has a second inductance, and wherein the second spiral routing stack is electrically coupled in series to the first spiral routing stack through the second conductive via.
20 . The integrated circuit package of claim 18 , wherein the first spiral routing stack comprises:
the first conductive trace embedded in a first dielectric layer of the first routing structure, wherein the first conductive trace has the first semicircular shape or the first semi-polygonal shape in the top-down view;
a second conductive trace embedded in a second dielectric layer of the first routing structure, wherein the second dielectric layer of the first routing structure is over the first dielectric layer of the first routing structure, wherein the second conductive trace has a second semicircular shape or a second semi-polygonal shape in the top-down view; and
a third conductive via embedded in the second dielectric layer of the first routing structure and connecting the first conductive trace to the second conductive trace, wherein in the top-down view, the first conductive trace and the second conductive trace form a circular shape or a polygonal shape.