Chip singulation assisted structures and methods for improving bonding interface quality
Integrated circuit (IC) structures, electronic modules, and methods of fabrication are described in which direct bonded interfaces are removed at corners or edges to counteract the potential for non-bonding or delamination. This can be accomplished during singulation, in which a side recess is formed through an entire thickness of an electronic component and into a direct bonded die, followed by final singulation of the IC structure.
1 . An integrated circuit structure comprising:
an electronic component including a first bonding surface;
a die including a second bonding surface bonded directly to the first bonding surface;
a side recess extending through an entire thickness of the electronic component and into the die;
wherein the side recess defines a recess sidewall extending through the entire thickness of the electronic component and a recess roof within the die; and
wherein the recess roof intersects with an outermost lateral sidewall of the die such that the outermost lateral sidewall is exterior to the recess sidewall.
2 . The integrated circuit structure of claim 1 , wherein the first bonding surface and the second bonding surface are hybrid bonded or fusion bonded together.
3 . The integrated circuit structure of claim 2 , wherein the die includes:
a semiconductor layer; and
a back-end-of-the-line (BEOL) build-up structure on the semiconductor layer;
wherein the recess roof is in the semiconductor layer.
4 . The integrated circuit structure of claim 3 , further comprising:
a second die including a third bonding surface bonded directly to the first bonding surface; and
a gap fill material laterally between the first die and the second die.
5 . The integrated circuit structure of claim 4 , further comprising:
a second side recess extending through the entire thickness of the electronic component and into the second die;
wherein the second side recess defines a second recess sidewall extending through the entire thickness of the electronic component and a second recess roof within the second die; and
wherein the second recess roof intersects with a second outermost lateral sidewall of the second die such the second outermost lateral sidewall is exterior to the second recess sidewall.
6 . The integrated circuit structure of claim 5 , wherein the second outermost lateral sidewall of the second die is parallel to the outermost lateral sidewall of the first die.
7 . The integrated circuit structure of claim 4 , further comprising a chiplet including a fourth bonding surface bonded directly to the first bonding surface, wherein the gap fill material is laterally between the chiplet and both the second die and the first die.
8 . The integrated circuit structure of claim 7 , wherein the side recess does not extend into the chiplet.
9 . The integrated circuit structure of claim 8 , wherein:
the electronic component comprises a first BEOL build-up structure;
the first BEOL build-up structure includes a first seal ring adjacent to the recess sidewall;
the die includes a second BEOL build-up structure; and
the second BEOL build-up structure includes a second seal ring adjacent to the recess sidewall;
wherein the first seal ring extends underneath the chiplet.
10 . The integrated circuit structure of claim 4 , wherein the die includes one or more chamfered corners, and the side recess does not include a chamfered corner along the outermost lateral sidewall of the die.
11 . The integrated circuit structure of claim 10 , wherein the die includes a seal ring adjacent to the recess sidewall, wherein the seal ring includes a chamfered corner adjacent to the recess sidewall.
12 . The integrated circuit structure of claim 3 , further comprising a gap fill material laterally surrounding the die, wherein the side recess extends into the gap fill material, and the recess roof is additionally formed in the gap fill material.
13 . The integrated circuit structure of claim 3 , wherein the electronic component is selected from the group consisting of a die and an interposer.
14 . The integrated circuit structure of claim 1 :
further comprising a local cavity extending through the entire thickness of the electronic component and into the die;
wherein the local cavity defines a cavity sidewall extending through the entire thickness of the electronic component and a cavity roof within the die; and
wherein the local cavity is completely surrounded by the electronic component and the die.
15 . The integrated circuit structure of claim 14 , wherein the local cavity is substantially filled with one or more cavity fill material layers.
16 . The integrated circuit structure of claim 1 , further comprising one or more recess fill material layers substantially filling the side recess.
17 . The integrated circuit structure of claim 16 , further comprising a liner layer spanning the side recess, the liner layer conformal to a contour and forming an outline along the recess sidewall and recess roof of the side recess, wherein the liner layer is between the one or more recess fill material layers and the side recess.
18 . The integrated circuit structure of claim 16 , further comprising:
a passivation layer spanning underneath the one or more recess fill material layers and the electronic component; and
a plurality of terminals underneath the passivation layer.
19 . An electronic module comprising:
a module substrate;
an integrated circuit structure mounted on the module substrate, the integrated circuit structure comprising:
an electronic component including a first bonding surface;
a die including a second bonding surface bonded directly to the first bonding surface;
a side recess extending through an entire thickness of the electronic component and into the die;
wherein the side recess defines a recess sidewall extending through the entire thickness of the electronic component and a recess roof within the die; and
wherein the recess roof intersects with an outermost lateral sidewall of the die such that the outermost lateral sidewall is exterior to the recess sidewall.
20 . The electronic module of claim 19 , further comprising an underfill material between the integrated circuit structure and the module substrate, wherein the underfill material fills the side recess.
21 . The electronic module of claim 20 , further comprising a gap fill material laterally surrounding the die, wherein the side recess extends into the gap fill material.
22 . The electronic module of claim 20 , wherein the first bonding surface and the second bonding surface are hybrid bonded or fusion bonded together.
23 . The electronic module of claim 20 :
further comprising a local cavity extending through the entire thickness of the electronic component and into the die;
wherein the local cavity defines a cavity sidewall extending through the entire thickness of the electronic component and a cavity roof within the die;
wherein the local cavity is completely surrounded by the electronic component and the die; and
wherein the underfill material fills the local cavity.
24 . The electronic module of claim 19 , further comprising:
one or more recess fill material layers substantially filling the side recess; and
an underfill material between the integrated circuit structure and the module substrate;
wherein the underfill material does not encroach inside the side recess.
25 . The electronic module of claim 19 :
further comprising a local cavity extending through the entire thickness of the electronic component and into the die;
an underfill material between the integrated circuit structure and the module substrate;
wherein the local cavity defines a cavity sidewall extending through the entire thickness of the electronic component and a cavity roof within the die;
wherein the local cavity is completely surrounded by the electronic component and the die; and
wherein the local cavity is substantially filled with one or more cavity fill material layers, and the underfill material does not encroach inside the local cavity.
26 . A method of forming an integrated circuit structure comprising:
directly bonding a die to an electronic component substrate;
encapsulating the die on the electronic component substrate with a gap fill material;
forming a side recess through an entire thickness of the electronic component substrate and into the die, wherein the side recess defines a recess sidewall extending through the entire thickness of the electronic component substrate and a recess roof within the die; and
sawing through the side recess to singulate the electronic component, wherein the recess roof intersects with an outermost lateral sidewall of the die such the outermost lateral sidewall is exterior to the recess sidewall.
27 . The method of claim 26 , wherein forming the side recess comprises laser drilling.
28 . The method of claim 27 , wherein directly bonding the die to the electronic component substrate comprises hybrid bonding or fusion bonding.
29 . The method of claim 26 , further comprising depositing one or more recess fill material layers in the side recess prior to sawing through the side recess to singulate the electronic component.
30 . An integrated circuit structure comprising:
an electronic component including a first bonding surface;
a die including a second bonding surface bonded directly to the first bonding surface;
a local cavity extending through an entire thickness of the electronic component and into the die;
wherein the local cavity defines a cavity sidewall extending through the entire thickness of the electronic component and a cavity roof within the die; and
wherein the local cavity is completely surrounded by the electronic component and the die.
31 . The integrated circuit structure of claim 30 , wherein the electronic component includes a first seal ring, and the die includes a second seal ring, and the local cavity extends through the electronic component and into the die outside of the first seal ring and the second seal ring.
32 . The integrated circuit structure of claim 30 , wherein the first bonding surface and the second bonding surface are hybrid bonded or fusion bonded together.
33 . The integrated circuit structure of claim 32 , wherein the die includes:
a semiconductor layer; and
a back-end-of-the-line (BEOL) build-up structure on the semiconductor layer;
wherein the cavity roof is in the semiconductor layer.
34 . The integrated circuit structure of claim 30 , wherein the local cavity is substantially filled with one or more cavity fill material layers.