Voltage regulating module design for the use of underfill
A voltage regulating module design is provided. In one aspect, a voltage regulating module (VRM) includes a first layer configured to output a regulated voltage that is based on a stepped down voltage, and a second layer stacked with the first layer, and a plurality of contacts, such as a ball grid array (BGA), on the first layer. The second layer includes a plurality of active components configured to provide the stepped down voltage to the first layer. The first and second layers have overlapping recesses, and the recess of the first layer has a larger footprint than the recess of the second layer. A plurality of the VRMS can be arranged to form an opening including a counterbore. A faster, such as a bolt, can be positioned in the opening. The first layer can have a larger clearance from the fastener positioned in the opening than the second layer.
1 . A voltage regulating module (VRM), comprising:
a first layer configured to output a regulated voltage that is based on a stepped down voltage, the first layer having a first recess;
a second layer stacked with the first layer, the second layer comprising a plurality of active components configured to receive a voltage, generate the stepped down voltage based on the voltage, and provide the stepped down voltage to the first layer, the second layer having a second recess that overlaps with the first recess, the first recess having a larger footprint than the second recess, the first and second recesses defining a curved opening that provides clearance for a fastener to be inserted through the curved opening; and
a plurality of contacts on the first layer and configured to output the regulated voltage,
wherein the plurality of contacts are encapsulated with an underfill, the underfill forming a fillet that extends from an edge of the first layer towards the fastener.
2 . The VRM of claim 1 , wherein the plurality of contacts includes a ball grid array.
3 . The VRM of claim 1 , further comprising a third layer stacked with the first and second layers, the third layer comprising plurality of active components.
4 . The VRM of claim 3 , wherein the third layer has a third recess having an area that is substantially the same as the area of the second recess.
5 . The VRM of claim 1 , wherein the first layer comprises a plurality of discrete components configured to multiply the current of the stepped down voltage.
6 . The VRM of claim 5 , wherein the discrete components comprise passive circuit elements.
7 . A multi-chip module, comprising:
a plurality of integrated circuit (IC) dies;
a plurality of voltage regulating modules (VRMs), wherein each VRM of the VRMs is stacked with a respective IC die of the plurality of IC dies; and
a plurality of fasteners located in curved openings between VRMs of the plurality of VRMs;
wherein a first VRM of the plurality of VRMs comprises:
a first layer configured to output a regulated voltage that is based on a stepped down voltage, the first layer having a first recess;
a second layer stacked with the first layer, the second layer comprising a plurality of active components configured to receive a voltage and provide the stepped down voltage to the first layer, the second layer having a second recess that overlaps with the first recess, the first layer having a larger clearance from a first fastener of the plurality of fasteners than the second layer, the first fastener being located in a first curved opening of the curved openings, the first curved opening being at least partly defined by the first recess and the second recess; and
a plurality of contacts on the first layer and electrically connected to a first IC die of the plurality of IC dies that is stacked with the first VRM, the plurality of contacts configured to provide the regulated voltage to the first IC die,
wherein the plurality of contacts are encapsulated with an underfill, the underfill forming a fillet that extends from an edge of the first layer towards the fastener.
8 . The multi-chip module of claim 7 , wherein the plurality of contacts includes a ball grid array.
9 . The multi-chip module of claim 7 , wherein the clearance of the first layer is configured to impede the underfill from clogging the first recess.
10 . The multi-chip module of claim 7 , wherein a distance that the fillet extends from the edge of the first layer towards the first fastener is less than a distance between the clearance of the first layer and the clearance of the second layer.
11 . The multi-chip module of claim 7 , wherein the first layer comprises a plurality of passive circuit elements configured to multiply the current of the stepped down voltage.
12 . The multi-chip module of claim 7 , wherein the plurality of fasteners comprise bolts.
13 . The multi-chip module of claim 7 , further comprising a cooling system configured to actively cool the VRMs.
14 . The multi-chip module of claim 7 , wherein a system on wafer (SoW) includes the IC dies.
15 . The multi-chip module of claim 14 , further comprising a thermal dissipation structure formed on a side of the SoW opposing the first and second layers.