Granted Patent B2

US 12,748,481 · App. 18/396,200 · Granted Sep 29, 2026

Inventors: Sungchang Park (Paju-si, KR); Byunghan An (Gumi-si, KR); Hyungseob Lim (Paju-si, KR)

Assignee: LG Display Co., Ltd.

G06F1/3265G06F1/3287G09G3/3225G09G3/3648G09G2310/08G09G2330/023G09G2340/0435

Abstract

Claims (44)

1 . A display device comprising:

a display panel; and

a plurality of source drivers configured to convert image data into a data voltage and provide the data voltage to the display panel,

wherein each of the plurality of source drivers includes a reception circuit configured to reconstruct at least one of the image data, control data, or a clock from a data packet received from a transmission circuit of a timing controller, and

a source output circuit configured to output the data voltage to the display panel,

wherein the display device includes a lock signal indicating an output stable state between the timing controller and the plurality of source drivers,

wherein the transmission circuit and the reception circuit are configured to be disabled in response to the lock signal being deactivated during a skip frame in a variable refresh rate mode operation, wherein the variable refresh rate mode operates at a first refresh rate during a first period, and a second refresh rate during a second period, the second refresh rate different from the first refresh rate,

wherein during the skip frame of the second period, the reception circuit of a first source driver in the plurality of source drivers is configured to be deactivated in response to a first lock signal from the transmission circuit, and provide a second lock signal to an adjacent second source driver in the plurality of source drivers, and the reception circuit of the adjacent second source driver is configured to be deactivated in response to the second lock signal during the skip frame, and

wherein, while the transmission circuit and the reception circuit are disabled during the skip frame, the source output circuit is configured to maintain and output a data voltage corresponding to image data latched at a last time during a refresh frame.

2 . The display device of claim 1 , wherein the timing controller includes the transmission circuit configured to:

generate the data packet including at least one of the image data, the control data, and the clock, and

transmit the data packet to the plurality of source drivers.

3 . The display device of claim 1 , wherein the transmission circuit and the reception circuit are configured to enter a sleep mode in response to the lock signal being deactivated during the skip frame.

4 . The display device of claim 1 , wherein the display device is configured to:

count a time upon entering the skip frame, and

activate the transmission circuit in response to the counted time reaching a reference time.

5 . The display device of claim 4 , wherein the transmission circuit is configured to transmit a data packet including at least a clock to the reception circuit when activated.

6 . The display device of claim 5 , wherein the reception circuit is configured to:

reconstruct the clock from the data packet; and

activate the lock signal in response to a phase and a frequency of an internal clock being fixed via clock training.

7 . The display device of claim 6 , wherein the transmission circuit is configured to enter the refresh frame in response to the activated the lock signal.

8 . The display device of claim 7 , wherein upon entering the refresh frame, the transmission circuit is configured to transmit the data packet including the image data, the control data, and the clock to the reception circuit.

9 . A method for operating a display device that includes a display panel and a plurality of source drivers configured to convert image data into a data voltage and provide the data voltage to the display panel,

wherein each of the plurality of source drivers includes a reception circuit configured to reconstruct at least one of the image data, control data, and a clock from a data packet received from a timing controller,

the method comprises:

providing a lock signal indicating an output stable state between the timing controller and the plurality of source drivers;

deactivating a transmission circuit of the timing controller and the reception circuit in response to the lock signal being deactivated during a skip frame in a variable refresh rate mode operation, wherein the variable refresh rate mode operates at a first refresh rate during a first period, and a second refresh rate during a second period, the second refresh rate different from the first refresh rate,

wherein during the skip frame of the second period, the reception circuit of a first source driver in the plurality of source drivers is configured to be deactivated in response to a first lock signal from the transmission circuit, and provide a second lock signal to an adjacent second source driver in the plurality of source drivers, and the reception circuit of the adjacent second source driver is configured to be deactivated in response to the second lock signal during the skip frame; and

while the transmission circuit and the reception circuit are deactivated during the skip frame, maintaining and outputting, by a source output circuit of each source driver, a data voltage corresponding to image data latched at a last time during a refresh frame.

10 . The method of claim 9 , wherein the method further comprises causing the transmission circuit and the reception circuit to enter a sleep mode in response to the lock signal being deactivated during the skip frame.

11 . The method of claim 9 , wherein the method further comprises counting a time upon entering the skip frame, and activating the transmission circuit in response to the counted time reaching a reference time.

12 . The method of claim 11 , wherein the method further comprises transmitting, by the transmission circuit, a data packet including at least a clock to the reception circuit when the transmission circuit is activated.

13 . The method of claim 12 , wherein the method further comprises:

reconstructing the clock from the data packet; and

activating the lock signal in response to a phase and a frequency of an internal clock being fixed via clock training.

14 . The method of claim 13 , wherein the method further comprises causing the transmission circuit to enter the refresh frame in response to the activated lock signal.

15 . A method for operating a display device, the display device including a display panel, the method comprising:

converting image data into data voltage, and providing the data voltage to the display panel; and

providing a lock signal indicating an output stable state between a timing controller and a source driver;

deactivating reconstruction of at least one of image data, control data, and a clock from a data packet received from the timing controller in response to the lock signal being deactivated during a skip frame in a variable refresh rate mode operation, wherein the variable refresh rate mode operates at a first refresh rate during a first period, and a second refresh rate during a second period, the second refresh rate different from the first refresh rate,

wherein during the skip frame of the second period, the reception circuit of a first source driver in the plurality of source drivers is configured to be deactivated in response to a first lock signal from the transmission circuit, and provide a second lock signal to an adjacent second source driver in the plurality of source drivers, and the reception circuit of the adjacent second source driver is configured to be deactivated in response to the second lock signal during the skip frame; and

while the reconstruction is deactivated during the skip frame, maintaining and outputting the data voltage corresponding to image data latched at a last time during a refresh frame.

16 . The method of claim 15 , wherein maintaining and outputting the data voltage comprises:

outputting the data voltage at a level corresponding to the data voltage latched at a last refresh frame while reconstruction of the image data, the control data, and the clock is deactivated.

Assignments (2)

Priority Claims (1)

Continuity (1)

References Cited (16)