Granted Patent B2

US 12,748,719 · App. 18/817,233 · Granted Sep 29, 2026

Inventors: Hung-Chang Kuo (Hsinchu City, TW); Wei-De Jeng (Hsinchu City, TW); Mao-Cheng Chiu (Hsinchu City, TW)

Assignee: MEDIATEK INC.

G06F13/4221G06F1/04H03K19/20G06F2213/0026

Abstract

Claims (26)

1 . A Peripheral Component Interconnect Express (PCIe) clock detection circuit comprising:

a clock detector configured to detect amplitude of a clock signal and generate a clock detection signal accordingly;

a clock receiver configured to generate a reference clock signal according to the clock signal;

a counter coupled to the clock receiver, configured to generate a counter signal according to the reference clock signal;

a multiplexer coupled to the counter, configured to generate a MUX output signal according to the counter signal and a reference signal; and

an AND gate coupled to the clock detector and the multiplexer, configured to generate a clock detection output signal according to the clock detection signal and the MUX output signal.

2 . The PCIe clock detection circuit of claim 1 , wherein the clock receiver is a buffer circuit.

3 . The PCIe clock detection circuit of claim 1 , wherein the clock detection signal is raised to a high level when the clock detector detects that the amplitude of the clock signal is above a threshold voltage.

4 . The PCIe clock detection circuit of claim 1 , wherein the counter signal is raised to a high level if the reference clock signal is continuous.

5 . The PCIe clock detection circuit of claim 1 , wherein the reference clock signal is identical to the clock signal in amplitude and frequency.

6 . The PCIe clock detection circuit of claim 1 , wherein the clock signal has a frequency of 100 MHz.

7 . The PCIe clock detection circuit of claim 1 , wherein the reference clock signal has a frequency of 100 MHz.

8 . The PCIe clock detection circuit of claim 1 , wherein the clock signal is a differential clock signal.

9 . A method for clock detection implemented by a Peripheral Component Interconnect Express (PCIe) clock detection circuit, the PCIe clock detection circuit comprising a clock detector, a clock receiver, a counter coupled to the clock receiver, a multiplexer coupled to the counter, and an AND gate coupled to the clock detector and the multiplexer, the method comprising:

detecting amplitude of a clock signal by the clock detector and generate a clock detection signal;

generating a reference clock signal by the clock receiver according to the clock signal;

generating a counter signal by the counter according to the reference clock signal;

generating a MUX output signal by the multiplexer according to the counter signal and a reference signal; and

generating a clock detection output signal by the AND gate according to the clock detection signal and the MUX output signal.

10 . The method of claim 9 , wherein the clock receiver is a buffer circuit.

11 . The method of claim 9 , wherein the counter signal is raised to a high level if the reference clock signal is continuous.

12 . The method of claim 9 , wherein the clock detection signal is raised to a high level when the clock detector detects that the amplitude of the clock signal is above a threshold voltage.

13 . The method of claim 9 , wherein the reference clock signal is identical to the clock signal in amplitude and frequency.

14 . The method of claim 9 , wherein the clock signal has a frequency of 100 MHz.

15 . The method of claim 9 , wherein the reference clock signal has a frequency of 100 MHz.

16 . The method of claim 9 , wherein the clock signal is a differential clock signal.

Assignments (1)

Continuity (2)

References Cited (11)