Reducing component database size for reduced run-set evaluation
Systems and methods parse integrated circuit (IC) design files to identify boundary conditions between components. The boundary conditions may correspond to connections between different components, at various levels of the IC, that may create antennas during one or more manufacturing processes. The identified boundary conditions may be extracted from the design files to generate lighter weight design files that eliminate parameters that are not associated with the boundary conditions. Design files for each component within a system may be parsed and checked for boundary conditions prior to delivery and integration to a top level design file. Thereafter, the top level may be executed with a run-set, such as to perform an antenna check.
1 . A computer-implemented method, comprising:
receiving a design file for a component of an integrated circuit (IC), the design file having a first quantity of data content;
determining, based on one or more indicators associated with the design file, one or more boundary conditions corresponding to connections between the component and one or more additional components of the IC;
extracting, from the design file, the one or more boundary conditions;
generating, using the extracted one or more boundary conditions, a skin design for the component representing the one or more boundary conditions of the component, the skin design having a second file size with less data content than a first file size;
generating, using at least the skin design, a top level skin design; and
executing, on the top level skin design, an antenna check.
2 . The computer-implemented method of claim 1 , further comprising:
receiving a run-set associated with an IC production process.
3 . The computer-implemented method of claim 1 , wherein the top level skin design includes respective skin designs for the component and the one or more additional components.
4 . The computer-implemented method of claim 1 , wherein the design file is at least one of an Open Artwork System Interchange Standard file or a Design Exchange Format file.
5 . The computer-implemented method of claim 1 , further comprising:
converting at least one of the skin design or the design file into a different file format.
6 . A computer-implemented method, comprising:
receiving a design file associated with a first integrated circuit (IC) component;
identifying, using one or more indicators of the design file, a boundary condition corresponding to a connection from the first IC component to a second IC component;
extracting the identified boundary condition; and
generating a skin design file including the boundary condition combined with at least one additional skin design file.
7 . The computer-implemented method of claim 6 , further comprising:
providing the skin design file to a top level integrator for inclusion within a top level skin design file.
8 . The computer-implemented method of claim 6 , wherein the design file is an Open Artwork System Interchange Standard (OASIS) file.
9 . The computer-implemented method of claim 8 , further comprising:
converting the OASIS file to a Design Exchange Format (DEF) file.
10 . The computer-implemented method of claim 9 , wherein the converting is performed prior to the identifying.
11 . The computer-implemented method of claim 6 , wherein the design file is a DEF file, the method further comprising:
converting the DEF file to an OASIS file.
12 . The computer-implemented method of claim 6 , further comprising:
receiving the skin design file for the first IC component;
receiving a second skin design file for the second IC component; and
merging the skin design file and the second skin design file into a hierarchical top level skin design file.
13 . The computer-implemented method of claim 12 , further comprising:
performing an antenna check on the top level skin design file.
14 . The computer-implemented method of claim 6 , wherein the skin design file is a smaller file than the design file.
15 . A system, comprising:
at least one processor; and
memory including instructions that, when executed by the at least one processor, cause the at least one processor to:
receive a design file associated with a first integrated circuit (IC) component;
identify, using one or more indicators of the design file, a boundary condition corresponding to a connection from the first IC component to a second IC component;
extract the boundary condition; and
generate a reduced design file including the boundary condition combined with at least one additional reduced design file.
16 . The system of claim 15 , wherein the design file is an Open Artwork System Interchange Standard (OASIS) file.
17 . The system of claim 16 , wherein the instructions when executed further cause the at least one processor to:
convert the OASIS file to a Design Exchange Format (DEF) file.
18 . The system of claim 17 , wherein converting the OASIS file is performed prior to identifying the boundary condition.
19 . The system of claim 15 , wherein the instructions when executed further cause the at least one processor to:
determine one or more locations on the first component associated with the connection to the second IC component.
20 . The system of claim 15 , wherein the instructions when executed further cause the at least one processor to:
receive the reduced design file; and
merge the reduced design file into a top level design file, the reduced design file replacing an associated full design file for the first IC component.