Scan driver and display device including the same
A scan driver includes a plurality of stages sequentially connected to each other. Each of the plurality of stages includes first and second output transistors and first to fourth control transistors. The second control transistor is connected between a second node and a first voltage terminal and to an input terminal and operates in response to a start signal or a previous carry signal provided through the input terminal. Each of the first and second output transistors and the first, third, and fourth control transistors is a first type, and the second control transistor is a second type different from the first type.
1 . A scan driver comprising:
a plurality of stages sequentially connected to each other, each of the plurality of stages including:
a first output transistor which is connected between an output terminal and a first voltage terminal, and operates in response to a potential of a first node;
a second output transistor which is connected between the output terminal and a second voltage terminal, and operates in response to a potential of a second node;
a first control transistor which is connected between an input terminal which receives a start signal or a previous carry signal from a previous stage and a third node, and operates in response to a clock signal provided through a clock terminal;
a second control transistor which is connected between the second node and the first voltage terminal, and operates in response to a potential of the third node, the second control transistor including:
a first electrode connected to the second node;
a second electrode connected to the first voltage terminal;
a top gate electrode directly connected to the third node; and
a bottom gate electrode directly connected to the first node without going through a capacitor,
a third control transistor which is connected between the top gate electrode and the bottom gate electrode, and operates in response to a first voltage provided through the first voltage terminal; and
a fourth control transistor which is connected between the second node and the second voltage terminal, and operates in response to the potential of the third node,
wherein each of the first and second output transistors and the first, third, and fourth control transistors is a first type,
wherein the second control transistor is a second type different from the first type.
2 . The scan driver of claim 1 , wherein each of the plurality of stages further comprises:
a first capacitor connected between the output terminal and the first node; and
a second capacitor connected between the second node and the second voltage terminal.
3 . The scan driver of claim 1 , wherein the first type is a P-type, and the second type is an N-type.
4 . The scan driver of claim 3 , wherein the second control transistor includes an oxide semiconductor layer, and
wherein each of the first and second output transistors and the first, third, and fourth control transistors includes a low-temperature polycrystalline silicon semiconductor layer.
5 . The scan driver of claim 1 , wherein a voltage level of the first voltage applied to the first voltage terminal is lower than a voltage level of a second voltage applied to the second voltage terminal.
6 . A scan driver comprising:
a plurality of stages sequentially connected to each other, each of the plurality of stages including:
a first output transistor including:
a first electrode connected to an output terminal;
a second electrode connected to a first voltage terminal; and
a third electrode connected to a first node;
a first capacitor connected between the output terminal and the first node;
a second output transistor including:
a first electrode connected to the output terminal;
a second electrode connected to a second voltage terminal; and
a third electrode connected to a second node;
a first control transistor including:
a first electrode connected to an input terminal;
a second electrode connected to a third node; and
a third electrode connected to a clock terminal;
a second control transistor including:
a first electrode connected to the second node;
a second electrode connected to the first voltage terminal;
a top gate electrode directly connected to the third node; and
a bottom gate electrode facing the top gate electrode and directly connected to the first node without going through a capacitor;
a third control transistor including:
a first electrode connected to the top gate electrode;
a second electrode connected to the bottom gate electrode; and
a third electrode connected to the first voltage terminal; and
a fourth control transistor including:
a first electrode connected to the second node;
a second electrode connected to the second voltage terminal; and
a third electrode connected to the third node.
7 . The scan driver of claim 6 , wherein each of the plurality of stages further includes:
a second capacitor connected between the second node and the second voltage terminal.
8 . The scan driver of claim 6 , wherien each of the first and second output transitors and the first, third, and fourth control transistors is a P-type, and
wherein the second control transistor is an N-type.
9 . The scan driver of claim 8 , wherein the second control transistor includes an oxide semiconductor layer, and
whereien each of the first and second output transistors and the first, third, and fourth control transistors includes a low-temperature polycrystalline silicon semiconductor layer.
10 . A display device comprising:
a display panel including a plurality of pixels;
a data driver which outputs data signals to the display panel; and
a scan driver which outputs scan signals to the display panel, the scan driver including:
a plurality of stages sequentially connected to each other, each of the plurality of stages including:
a first output transistor including:
a first electrode connected to an output terminal;
a second electrode connected to a first voltage terminal; and
a third electrode connected to a first node;
a second output transistor including:
a first electrode connected to the output terminal;
a second electrode connected to a second voltage terminal; and
a third electrode connected to a second node;
a first control transistor including:
a first electrode connected to an input terminal;
a second electrode connected to a third node; and
a third electrode connected to a clock terminal;
a second control transistor including:
a first electrode connected to the second node;
a second electrode connected to the first voltage terminal;
a top gate electrode directly connected to the third node; and
a bottom gate electrode directly connected to the first node without going through a capacitor,
a third control transistor including:
a first electrode connected to the top gate electrode;
a second electrode connected to the bottom gate electrode; and
a third electrode connected to the first voltage terminal; and
a fourth control transistor including:
a first electrode connected to the second node;
a second electrode connected to the second voltage terminal; and
a third electrode connected to the third node,
wherein each of the first and second output transistors and the first, third, and fourth control transistors is a P-type, and
wherein the second control transistor is an N-type.