Scannable SRAM
A scannable memory cell includes an amplifier configured in a positive feedback loop, with the amplifier output coupled to the scan output SO terminal. The memory cell further has a data access switch coupled between the amplifier output and the bit line BL terminal, and a scan access switch coupled between the amplifier input and the scan input SI terminal. Control terminals of both switches are coupled to the word line WL and scan control SC line terminals, respectively. Some implementations further include a scan loop switch, controlled by the scan control SC terminal, and configured to interrupt the positive feedback loop when the memory cell is in scan mode. Other implementations include a scan out SO buffer or inverter with increased drive strength.
1 . A scannable memory cell, with a bit line BL terminal, a word line WL terminal, a scan control line SC terminal, a scan input SI terminal, and a scan output SO terminal, the scannable memory cell comprising:
an amplifier with an amplifier input and a first amplifier output, configured in a positive feedback loop, and wherein the first amplifier output or a second amplifier output is coupled with the scan output SO terminal;
a first data access switch coupled between the first amplifier output and the bit line BL terminal, and with a control terminal coupled with the word line WL terminal;
a first scan access switch coupled between the amplifier input and the scan input SI terminal, and with a control terminal coupled with the scan control line SC terminal; and
a first scan loop switch coupled in the positive feedback loop between the amplifier input and the first amplifier output, and having a control terminal coupled with the scan control line SC terminal.
2 . The scannable memory cell of claim 1 , wherein:
the amplifier comprises a first inverting gate with an input coupled with the amplifier input and with an output coupled with an input of a second inverting gate, wherein the second inverting gate has an output coupled with the first amplifier output;
the scannable memory cell further comprises a complementary bit line /BL terminal; and
the scannable memory cell further comprises a second data access switch coupled between the output of the first inverting gate and the complementary bit line /BL terminal, and with a control terminal coupled with the word line WL terminal.
3 . The scannable memory cell of claim 2 , wherein:
the first inverting gate includes a CMOS inverter;
the second inverting gate includes a CMOS inverter; and
the first data access switch, the second data access switch, and the first scan access switch each include a pass transistor.
4 . The scannable memory cell of claim 3 , wherein the first scan loop switch includes a pass transistor.
5 . The scannable memory cell of claim 4 , wherein:
the first scan loop switch is de-asserted when the scan control line SC terminal is asserted, and the first scan access switch is asserted when the scan control line SC terminal is asserted.
6 . The scannable memory cell of claim 2 , wherein the amplifier further comprises a third inverting gate, with an input coupled with the output of the first inverting gate, and with an output coupled with the second amplifier output, and wherein the third inverting gate has a drive strength greater than a drive strength of the second inverting gate.
7 . The scannable memory cell of claim 1 , further comprising:
a second word line WL 2 terminal;
a second bit line BL 2 terminal; and
a second data access switch coupled between the first amplifier output and the second bit line BL 2 terminal, and with a control terminal coupled with the second word line WL 2 terminal.
8 . The scannable memory cell of claim 1 , further comprising:
a search line SL terminal;
a match line ML terminal; and
a combinational logic circuit coupled with the match line ML terminal, and with a first input coupled with the first amplifier output and a second input coupled with the search line SL terminal, wherein the combinational logic circuit compares a value of the first amplifier output with a value of the search line SL terminal.
9 . A method of using a scannable memory cell, the scannable memory cell including a buffer, a data access switch controlled by a word line WL, a scan access switch controlled by a scan control line SC and coupled between an input of the buffer and a scan input SI, and a scan loop switch controlled by the scan control line SC and coupled between an output of the buffer and the input of the buffer, the method comprising:
determining a mode from a signal on the scan control line SC and a signal on the word line WL;
upon determining that the mode is a data access mode, asserting the data access switch to couple the buffer with a bit line BL;
upon determining that the mode is not a data access mode, de-asserting the data access switch to decouple the buffer from the bit line BL;
upon determining that the mode is a scan mode, asserting the scan access switch to couple the input of the buffer with the scan input source SI and interrupting a positive feedback loop to decouple a buffer input from a buffer output; and
upon determining that the mode is not a scan mode, de-asserting the scan access switch to decouple the input of the buffer from the scan input source SI and restoring the positive feedback loop to couple the buffer input to the buffer output.