IP Library › Granted Patent US 12,749,975
Granted Patent B2
US 12,749,975 · App. 18/650,411 · Granted Sep 29, 2026

Light-load recovery in a multi-level converter

Inventor: Gregory Szczeszynski (Nashua, NH)
Assignee: Murata Manufacturing Co., Ltd.
H02M3/158H02M1/0095H02M1/14
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Quick Facts
Patent No.
US 12,749,975
App. No.
18/650,411
Granted
Sep 29, 2026
Kind
B2
Abstract

Circuits and methods that solve the light-load problem of a multi-level converter by generating a ripple signal in the control loop of the multi-level converter that causes a large output current ripple during light load conditions. This added current ripple does not change the average output current but does create a temporary positive and negative current that can be used to balance and charge/discharge the fly capacitors of the multi-level converter. An alternative approach is to add extra switching cycles for the fly capacitors when the output ripple current crosses zero.

Claims (47)

1 . A multi-level converter including:

an M-level converter cell comprising:

an input terminal;

a set of switches series-coupled between a voltage source and a reference voltage, wherein the set of switches has a switching frequency;

an output terminal coupled to an innermost pair of the set of switches and configured to be coupled to an inductor;

switch control inputs coupled to the set of switches; and

at least one fly capacitor coupled in series with certain respective switches and in parallel with switches situated in between the respective switches;

wherein the M-level converter cell is configured to transform an input voltage applied to the input terminal to an output voltage on the output terminal in response to control signals on the switch control inputs;

a controller coupled to the switch control inputs and configured to couple to the inductor, the controller configured to monitor an output of the M-level converter cell and dynamically generate a set of switch control input values to the M-level converter cell in response to such monitoring; and

a sub-harmonic signal generator coupled to the controller and configured to selectively inject a sub-harmonic signal into a signal path of the controller, wherein the sub-harmonic signal has a frequency about one-half or less than one-half the switching frequency of the set of switches.

2 . The multi-level converter of claim 1 , wherein the controller includes a comparison device having an input coupled to the inductor, and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path between the inductor and the comparison device.

3 . The multi-level converter of claim 1 , wherein the controller includes a comparison device having a reference voltage input, and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal at the reference voltage input.

4 . The multi-level converter of claim 1 , wherein the controller includes a compensation circuit, and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path before or after the compensation circuit.

5 . A multi-level converter comprising;

an M-level converter cell comprising:

an input terminal;

a set of switches series-coupled between a voltage source and a reference voltage;

an output terminal coupled to an innermost pair of the set of switches and configured to be coupled to an inductor;

switch control inputs coupled to the set of switches; and

at least one fly capacitor coupled in series with certain respective switches and in parallel with switches situated in between the respective switches;

wherein the M-level converter cell is configured to transform an input voltage applied to the input terminal to an output voltage on the output terminal in response to control signals on the switch control inputs;

a controller coupled to the switch control inputs and configured to couple to the inductor, the controller configured to monitor an output of the M-level converter cell and dynamically generate a set of switch control input values to the M-level converter cell in response to such monitoring; and

a sub-harmonic signal generator coupled to the controller and configured to selectively inject a sub-harmonic signal into a signal path of the controller, wherein the sub-harmonic signal enables charge balancing of the at least one fly capacitor.

6 . The multi-level converter of claim 1 , wherein the controller includes a pulse-width modulation generator, and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path after the pulse-width modulation generator.

7 . The multi-level converter of claim 1 , wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal when an average current through the inductor is approximately zero amps or when a light load is present on the output terminal.

8 . The multi-level converter of claim 1 , wherein the sub-harmonic signal creates temporary positive and negative currents sufficient to enable charge balancing of the at least one fly capacitor.

9 . The multi-level converter of claim 1 , wherein the sub-harmonic signal is an AC waveform having an average voltage of zero.

10 . The multi-level converter of claim 1 , wherein the switch control inputs include a pulse-width modulated signal, and wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal by altering a timing of the pulse-width modulated signal.

11 . A multi-level converter comprising:

an M-level converter cell comprising:

an input terminal;

a set of switches series-coupled between a voltage source and a reference voltage;

an output terminal coupled to an innermost pair of the set of switches and configured to be coupled to an inductor;

switch control inputs coupled to the set of switches; and

at least one fly capacitor coupled in series with certain respective switches and in parallel with switches situated in between the respective switches;

wherein the M-level converter cell is configured to transform an input voltage applied to the input terminal to an output voltage on the output terminal in response to control signals on the switch control inputs;

a controller coupled to the switch control inputs and configured to couple to the inductor, the controller configured to monitor an output of the M-level converter cell and dynamically generate a set of switch control input values to the M-level converter cell in response to such monitoring; and

a sub-harmonic signal generator coupled to the controller and configured to selectively inject a sub-harmonic signal into a signal path of the controller, wherein the sub-harmonic signal generator is configured to scale the sub-harmonic signal as a function of the absolute value of an average current through the inductor to obtain a scaled sub-harmonic signal and inject the scaled sub-harmonic signal.

12 . The multi-level converter of claim 11 , wherein the set of switches has a switching frequency, and the sub-harmonic signal has a frequency about one-half or less than one-half the switching frequency of the set of switches.

13 . The multi-level converter of claim 11 , wherein the sub-harmonic signal is an AC waveform.

14 . The multi-level converter of claim 11 , wherein the controller is further configured to add an extra charging cycle near or at a zero-current crossing point after a discharging cycle, and add an extra discharging cycle near or at a zero-current crossing point after a charging cycle.

15 . The multi-level converter of claim 11 , wherein the controller includes a compensation circuit, and wherein the sub-harmonic signal generator is configured to inject the scaled sub-harmonic signal in the signal path before or after the compensation circuit.

16 . The multi-level converter of claim 11 , wherein the controller includes a pulse-width modulation generator, and wherein the sub-harmonic signal generator is configured to selectively inject the scaled sub-harmonic signal in the signal path after the pulse-width modulation generator.

17 . The multi-level converter of claim 5 , wherein the controller includes a compensation circuit, and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path before or after the compensation circuit.

18 . The multi-level converter of claim 5 , wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal when an average current through the inductor is approximately zero amps or when a light load is present on the output terminal.

19 . The multi-level converter of claim 5 , wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal by altering a timing of a digital waveform generated by the controller that controls switching of the set of switches.

20 . The multi-level converter of claim 5 , wherein the sub-harmonic signal is an AC waveform having an average voltage of zero.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2026
From: PSEMI CORPORATION
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 075226/0081 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2026
From: SZCZESZYNSKI, GREGORY
To: PSEMI CORPORATION
Reel/Frame 075946/0031 →
Continuity (4)
Continuation PCTUS2022078920 · Oct 28, 2022
Continuation 17560683 · Dec 23, 2021
Provisional Application 63276962 · Nov 8, 2021
Related Publication 20240356442A1 · Oct 24, 2024
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