Display device
A display device includes non-folding areas, at least one folding area between the non-folding areas and configured to be transformed into a bent shape and a planar shape, and a display panel emitting light for displaying an image. A circuit layer of the display panel includes light-emitting pixel drivers, gate lines, and a gate-driving circuit including stages electrically connected to the gate lines. Each of the stages includes a first buffer transistor and a second buffer transistor. A channel portion of each of the first buffer transistor and the second buffer transistor in the at least one folding area has a comb shape formed by one or more slits that extend in a direction in which the first electrode portion and the second electrode portion face each other and are arranged in parallel with each other.
1 . A display device comprising:
a display panel configured to emit light for displaying an image, and comprising:
non-folding areas for maintaining a planar shape;
at least one folding area between the non-folding areas, and configured to be transformed between a bent shape and a planar shape;
a substrate comprising a display area in which emission areas are arranged, and a non-display area around the display area;
an element layer comprising light-emitting elements in the emission areas; and
a circuit layer between the element layer and the substrate, and comprising:
light-emitting pixel drivers respectively electrically connected to the light-emitting elements;
gate lines for transmitting gate signals to the light-emitting pixel drivers; and
a gate-driving circuit comprising stages electrically connected to the gate lines and comprising a first buffer transistor and a second buffer transistor connected in series between a first gate level voltage line and a second gate level voltage line,
wherein the first buffer transistor and the second buffer transistor comprise a channel portion, a first electrode portion connected to one side of the channel portion, a second electrode portion connected to another side of the channel portion, and a gate electrode overlapping the channel portion above an insulating layer covering the channel portion, and
wherein the channel portion in the at least one folding area has a comb shape of one or more slits extending in parallel in a direction in which the first electrode portion and the second electrode portion face each other.
2 . The display device of claim 1 , wherein the channel portion in the at least one folding area comprises two or more splits at respective sides of the one or more slits, and
wherein a width of the two or more splits is greater than a width of the one or more slits.
3 . The display device of claim 2 , wherein a part of the display area overlaps the at least one folding area, and
wherein a part of the non-display area overlaps the at least one folding area.
4 . The display device of claim 2 , wherein the at least one folding area is configured to be transformed by in-folding or out-folding.
5 . The display device of claim 1 , wherein the stages further comprise:
a first buffer input electrode electrically connected to the first gate level voltage line and to the first electrode portion of the first buffer transistor;
a second buffer input electrode electrically connected to the second gate level voltage line and to the first electrode portion of the second buffer transistor; and
a buffer output electrode electrically connected between at least one of the gate lines and the second electrode portion of the first buffer transistor and the second electrode portion of the second buffer transistor,
wherein the first buffer input electrode, the second buffer input electrode, and the buffer output electrode in the at least one folding area has a mesh shape of two or more through grooves arranged in parallel.
6 . The display device of claim 5 , wherein the channel portion in the non-folding areas has a planar shape other than the comb shape, and
wherein the first buffer input electrode, the second buffer input electrode, and the buffer output electrode in the non-folding areas has a planar shape other than the mesh shape.
7 . The display device of claim 5 , wherein the channel portion in the non-folding areas has the comb shape, and
wherein the first buffer input electrode, the second buffer input electrode, and the buffer output electrode in the non-folding areas has the mesh shape.
8 . The display device of claim 5 , wherein the circuit layer further comprises:
a first semiconductor layer above the substrate;
a first gate-insulating layer covering the first semiconductor layer;
a first gate conductive layer above the first gate-insulating layer;
a second gate-insulating layer covering the first gate conductive layer;
a second gate conductive layer above the second gate-insulating layer; and
a first interlayer insulating layer covering the second gate conductive layer,
wherein the channel portion, the first electrode portion, and the second electrode portion are in the first semiconductor layer, and
wherein the gate electrode is in the first gate conductive layer.
9 . The display device of claim 8 , wherein the circuit layer further comprises:
a second semiconductor layer above the first interlayer insulating layer;
a third gate-insulating layer covering the second semiconductor layer;
a third gate conductive layer above the third gate-insulating layer;
a second interlayer insulating layer covering the third gate conductive layer;
a first source-drain conductive layer above the second interlayer insulating layer;
a first planarization layer covering the first source-drain conductive layer;
a second source-drain conductive layer above the first planarization layer; and
a second planarization layer covering the second source-drain conductive layer, and
wherein the first buffer input electrode, the second buffer input electrode, and the buffer output electrode are in the first source-drain conductive layer or the second source-drain conductive layer.
10 . The display device of claim 9 , wherein one of the light-emitting pixel drivers comprises:
a first transistor electrically connected between a first node and a second node;
a pixel capacitor electrically connected between a first power line and a third node;
a second transistor electrically connected between a data line for transmitting a data signal and the first node;
a third transistor electrically connected between the second node and the third node;
a fourth transistor electrically connected between a gate initialization voltage line for transmitting a gate initialization voltage and the third node;
a fifth transistor electrically connected between the first power line and the first node;
a sixth transistor electrically connected between the second node and a fourth node;
a seventh transistor electrically connected between an anode initialization voltage line for transmitting an anode initialization voltage and the fourth node; and
an eighth transistor electrically connected between a bias voltage line for transmitting a bias voltage and the first node,
wherein the first node is electrically connected to a first electrode of the first transistor,
wherein the second node is electrically connected to a second electrode of the first transistor,
wherein the third node is electrically connected to a gate electrode of the first transistor,
wherein the fourth node is electrically connected to one of the light-emitting elements,
wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor comprise a channel portion, a first electrode portion, and a second electrode portion in the first semiconductor layer, and
wherein the third transistor and the fourth transistor comprise a channel portion, a first electrode portion, and a second electrode portion in the second semiconductor layer.
11 . The display device of claim 10 , wherein the gate lines comprise:
scan write lines for transmitting a scan write signal;
scan initialization lines for transmitting a scan initialization signal;
gate control lines for transmitting a gate control signal;
emission control lines for transmitting an emission control signal; and
bias control lines for transmitting a bias control signal,
wherein the second transistor is configured to be turned on by the scan write signal,
wherein the third transistor is configured to be turned on by the gate control signal,
wherein the fourth transistor is configured to be turned on by the scan initialization signal,
wherein the fifth transistor and the sixth transistor are configured to be turned on by the emission control signal, and
wherein the seventh transistor and the eighth transistor are configured to be turned on by the bias control signal.
12 . An electronic device comprising:
a lower cover;
a cover window above the lower cover; and
a display device for displaying an image between the lower cover and the cover window, and comprising a display panel configured to emit light for displaying an image, the display panel comprising:
non-folding areas maintaining a planar shape;
at least one folding area between the non-folding areas, and configured to transform between a bent shape and a planar shape;
a substrate comprising a display area in which emission areas are arranged, and a non-display area around the display area;
an element layer comprising light-emitting elements in the emission areas above the substrate; and
a circuit layer between the element layer and the substrate, and comprising:
light-emitting pixel drivers respectively electrically connected to the light-emitting elements;
gate lines for transmitting gate signals to the light-emitting pixel drivers; and
a gate-driving circuit comprising stages electrically connected to the gate lines, the stages comprising:
a first buffer transistor and a second buffer transistor connected in series between a first gate level voltage line and a second gate level voltage line;
a first buffer input electrode electrically connected to the first gate level voltage line and a first electrode portion of the first buffer transistor;
a second buffer input electrode electrically connected to the second gate level voltage line and a first electrode portion of the second buffer transistor; and
a buffer output electrode electrically connected between at least one of the gate lines and a second electrode portion of the first buffer transistor and a second electrode portion of the second buffer transistor,
wherein the gate lines are electrically connected to the buffer output electrodes, and
wherein the first buffer input electrode, the second buffer input electrode, and the buffer output electrode in the at least one folding area has a mesh shape of two or more through grooves arranged in parallel.
13 . The electronic device of claim 12 , wherein the first buffer transistor and the second buffer transistor comprises a channel portion, a first electrode portion connected to one side of the channel portion, a second electrode portion connected to another side of the channel portion, and a gate electrode overlapping the channel portion above an insulating layer covering the channel portion, and
wherein the channel portion of the first buffer transistor and the second buffer transistor in the at least one folding area has a comb shape of one or more slits extending in parallel in a direction in which the first electrode portion and the second electrode portion face each other.
14 . The electronic device of claim 13 , wherein the channel portion in the at least one folding area comprises two or more splits at respective sides of the one or more slits, and
wherein a width of the two or more splits is greater than a width of the one or more slits.
15 . The electronic device of claim 13 , wherein the channel portion in the non-folding areas has a planar shape other than the comb shape, and
wherein the first buffer input electrode, the second buffer input electrode, and the buffer output electrode in the non-folding areas has a planar shape other than the mesh shape.
16 . The electronic device of claim 13 , wherein the channel portion in the non-folding areas has the comb shape, and
wherein the first buffer input electrode, the second buffer input electrode, and the buffer output electrode in the non-folding areas has the mesh shape.
17 . The electronic device of claim 13 , wherein the circuit layer further comprises:
a first semiconductor layer above the substrate;
a first gate-insulating layer covering the first semiconductor layer;
a first gate conductive layer above the first gate-insulating layer;
a second gate-insulating layer covering the first gate conductive layer;
a second gate conductive layer above the second gate-insulating layer;
a first interlayer insulating layer covering the second gate conductive layer;
a second semiconductor layer above the first interlayer insulating layer;
a third gate-insulating layer covering the second semiconductor layer;
a third gate conductive layer above the third gate-insulating layer;
a second interlayer insulating layer covering the third gate conductive layer;
a first source-drain conductive layer above the second interlayer insulating layer;
a first planarization layer covering the first source-drain conductive layer;
a second source-drain conductive layer above the first planarization layer; and
a second planarization layer covering the second source-drain conductive layer, and
wherein the first buffer input electrode, the second buffer input electrode, and the buffer output electrode are in the first source-drain conductive layer or the second source-drain conductive layer.
18 . The electronic device of claim 17 , wherein the gate electrode is in the first gate conductive layer.
19 . The electronic device of claim 17 , wherein the gate lines comprise:
scan write lines for transmitting a scan write signal;
scan initialization lines for transmitting a scan initialization signal;
gate control lines for transmitting a gate control signal;
emission control lines for transmitting an emission control signal; and
bias control lines for transmitting a bias control signal.
20 . The electronic device of claim 19 , wherein one of the light-emitting pixel drivers comprises:
a first transistor electrically connected between a first node and a second node;
a pixel capacitor electrically connected between a first power line and a third node;
a second transistor electrically connected between a data line for transmitting a data signal and the first node;
a third transistor electrically connected between the second node and the third node;
a fourth transistor electrically connected between a gate initialization voltage line for transmitting a gate initialization voltage and the third node;
a fifth transistor electrically connected between the first power line and the first node;
a sixth transistor electrically connected between the second node and a fourth node;
a seventh transistor electrically connected between an anode initialization voltage line for transmitting an anode initialization voltage and the fourth node; and
an eighth transistor electrically connected between a bias voltage line for transmitting a bias voltage and the first node,
wherein the first node is electrically connected to a first electrode of the first transistor,
wherein the second node is electrically connected to a second electrode of the first transistor,
wherein the third node is electrically connected to a gate electrode of the first transistor,
wherein the fourth node is electrically connected to one of the light-emitting elements,
wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor comprise a channel portion, a first electrode portion, and a second electrode portion in the first semiconductor layer,
wherein the third transistor and the fourth transistor comprise a channel portion, a first electrode portion, and a second electrode portion in the second semiconductor layer,
wherein the second transistor is configured to be turned on by the scan write signal,
wherein the third transistor is configured to be turned on by the gate control signal,
wherein the fourth transistor is configured to be turned on by the scan initialization signal,
wherein the fifth transistor and the sixth transistor are configured to be turned on by the emission control signal, and
wherein the seventh transistor and the eighth transistor are configured to be turned on by the bias control signal.