MRAM device with tunnel barrier overhang
A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack. A semiconductor device is provided. The semiconductor device including a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack, where the tunneling barrier comprises a center portion and two outer portions, where the center portion is on an upper horizontal portion of the reference layer, and the two outer portions are on a slanted upper surface of an encapsulation layer surrounding the reference layer. Forming a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack.
1 . A semiconductor device comprising:
a magnetic tunnel junction (MTJ) stack, wherein a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack; and
a first encapsulation layer located around the reference layer, wherein the first encapsulation layer has an interior vertical side surface that is in direct contact with the reference layer, wherein the tunnel barrier extends laterally past an outer vertical side surface of the first encapsulation layer, wherein the interior vertical side surface and the outer vertical side surfaces are located on opposite sides of the first encapsulation layer, wherein the first encapsulation layer has a slanted upper surface.
2 . The semiconductor device according to claim 1 , further comprising:
the MTJ stack comprises vertically aligned layers of a top electrode, a free layer, the tunneling barrier, the reference layer and a bottom electrode.
3 . The semiconductor device according to claim 2 , wherein the free layer is wider than the reference layer.
4 . The semiconductor device according to claim 2 , wherein a width of the free layer is equal to a width of the tunneling barrier.
5 . The semiconductor device according to claim 1 , wherein a lowermost portion of the tunneling barrier is below an uppermost portion of the reference layer.
6 . The semiconductor device according to claim 2 , wherein a lowermost portion of the free layer is below an uppermost portion of the reference layer.
7 . The semiconductor device according to claim 2 , further comprising:
a second encapsulation layer surrounding vertical side surfaces of the free layer and the tunneling barrier.
8 . The semiconductor device according to claim 2 , further comprising:
a first inter-layer dielectric surrounding the bottom electrode;
a second inter-layer dielectric surrounding the reference layer;
a third inter-layer dielectric surrounding the free layer and the tunneling barrier; and
a fourth inter-layer dielectric surrounding the top electrode.
9 . A semiconductor device comprising:
a magnetic tunnel junction (MTJ) stack, wherein a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack, wherein the tunneling barrier comprises a center portion and two outer portions, wherein the center portion is on an upper horizontal portion of the reference layer; and
a first encapsulation layer located around the reference layer, wherein the first encapsulation layer has an interior vertical side surface that is in direct contact with the reference layer, wherein the tunnel barrier extends laterally past an outer vertical side surface of the first encapsulation layer, wherein the interior vertical side surface and the outer vertical side surfaces are located on opposite sides of the first encapsulation layer, wherein the first encapsulation layer has a slanted upper surface.
10 . The semiconductor device according to claim 9 , further comprising:
the MTJ stack comprises vertically aligned layers of a top electrode, a free layer, the tunneling barrier, the reference layer and a bottom electrode.
11 . The semiconductor device according to claim 10 , wherein the free layer is wider than the reference layer.
12 . The semiconductor device according to claim 10 , wherein a width of the free layer is equal to a width of the tunneling barrier.
13 . The semiconductor device according to claim 9 , wherein a lowermost portion of the tunneling barrier is below an uppermost portion of the reference layer.
14 . The semiconductor device according to claim 10 , wherein a lowermost portion of the free layer is below an uppermost portion of the reference layer.
15 . The semiconductor device according to claim 10 , further comprising:
a second encapsulation layer surrounding vertical side surfaces of the free layer and the tunneling barrier.
16 . The semiconductor device according to claim 10 , further comprising:
a first inter-layer dielectric surrounding the bottom electrode;
a second inter-layer dielectric surrounding the reference layer;
a third inter-layer dielectric surrounding the free layer and the tunneling barrier; and
a fourth inter-layer dielectric surrounding the top electrode.
17 . A method comprising:
forming a magnetic tunnel junction (MTJ) stack, wherein a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack; and
forming an encapsulation layer located around the reference layer, wherein the encapsulation layer has an interior vertical side surface that is in direct contact with the reference layer, wherein the tunnel barrier extends laterally past an outer vertical side surface of the encapsulation layer, wherein the interior vertical side surface and the outer vertical side surfaces are located on opposite sides of the encapsulation layer, wherein the first encapsulation layer has a slanted upper surface.
18 . The method according to claim 17 , wherein the tunneling barrier comprises a center portion and two outer portions, wherein the center portion is on an upper horizontal portion of the reference layer, and the two outer portions are on a slanted upper surface of an encapsulation layer surrounding the reference layer.