Field effect transistor with backside source/drain
A semiconductor device includes a nanostructure field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extends vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region extends below a bottom surface of the gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.
1 . A semiconductor device comprising:
an insulator layer;
a transistor upon the insulator layer, the transistor includes one or more channel regions, a first source or drain (S/D) region upon the insulator layer and connected to the one or more channel regions, and a second S/D region that extends below a top surface of the insulator layer, wherein a top surface of the first S/D region is below a top surface of the second S/D region; and
a liner upon a section of the insulator layer, the liner comprising a front portion in contact with a front surface of the second S/D region and a rear portion in contact with a rear surface of the second S/D region.
2 . The semiconductor device of claim 1 , wherein a bottom surface of the second S/D region is coplanar with a bottom surface of the insulator layer.
3 . The semiconductor device according to claim 1 , further comprising:
a frontside S/D contact connected to the top surface of the first S/D region.
4 . The semiconductor device according to claim 1 , further comprising:
a backside S/D contact connected to a bottom surface of the second S/D region.
5 . The semiconductor device according to claim 4 , further comprising:
a backside rail connected to a bottom surface of the backside S/D contact.
6 . The semiconductor device of claim 4 , wherein the second S/D region wraps around a perimeter of the backside S/D contact.
7 . The semiconductor device of claim 4 , wherein the first S/D region is formed of a first material and wherein the second S/D region is formed of a second material different than the first material.
8 . The semiconductor device according to claim 1 , wherein the transistor is a gate all around nanosheet structure that includes a plurality of channel regions each surrounded by one work function metal gate.
9 . A transistor comprising:
one or more channel regions;
a single gate that is around each of the one or more channel regions;
a first source or drain (S/D) region connected to the one or more channel regions; and
a second S/D region connected to the one or more channel regions, wherein a bottom surface of the second S/D region is below a bottom surface of the single gate, and wherein a top surface of the first S/D region is below a top surface of the second S/D region.
10 . The transistor of claim 9 , wherein the bottom surface of the second S/D region is coplanar with a backside interlayer dielectric.
11 . The transistor according to claim 9 , further comprising:
a frontside S/D contact connected to the top surface of the first S/D region.
12 . The transistor according to claim 9 , further comprising:
a backside S/D contact connected to the bottom surface of the second S/D region.
13 . The transistor according to claim 12 , further comprising:
a backside rail connected to a bottom surface of the backside S/D contact.
14 . The transistor of claim 12 , wherein the second S/D region wraps around a perimeter of the backside S/D contact.
15 . The transistor of claim 12 , wherein the first S/D region is formed of a first material and wherein the second S/D region is formed of a second material different than the first material.
16 . The transistor according to claim 9 , wherein the transistor is a gate all around nanosheet structure that includes a plurality of channel regions each surrounded by one work function metal gate.
17 . A semiconductor device comprising:
nanosheet channels;
a gate around each of the nanosheet channels;
a first source or drain (S/D) region connected to the nanosheet channels and upon an insulator layer;
a second S/D region connected to the nanosheet channels and that extends through the insulator layer, wherein a top surface of the first S/D region is below a top surface of the second S/D region;
an interlayer dielectric upon the insulator layer, upon the first S/D region, and upon the second S/D region; and
a liner upon the insulator layer and connected to solely the second S/D region.