Semiconductor device and method for manufacturing same
There is provided a semiconductor device of a chip-on-chip structure having a support semiconductor chip, first and second chip blocks supported and connected on one surface of the support semiconductor chip and an insulator arranged between the first and second chip blocks. The first and second chip blocks each include one or a plurality of semiconductor chips having an active surface nearly parallel with the one surface of the support semiconductor chip. Within the insulator, an intralevel wiring is arranged on a wiring plane as a plane including an inactive or active surface of any of the semiconductor chips structuring the first or second chip block.
1. A semiconductor device comprising:
a support semiconductor chip;
first and second chip blocks supported and connected on one surface of the support semiconductor chip and each including one or a plurality of semiconductor chips having an active surface substantially parallel with the one surface of the support semiconductor chip;
an insulator arranged between the first and second chip blocks;
an intralevel wiring arrangement within or on a surface of the insulator, on at least one wiring plane that includes an inactive or active surface of any of the semiconductor chips constituting the first or second chip blocks,
wherein the intralevel wiring arrangement includes first and second intralevel wirings respectively arranged on first and second wiring planes in the same plane.
2. A semiconductor device according to claim 1 , wherein the active or inactive surface of any of the semiconductor chip constituting the first chip block and the active or inactive surface of any of the semiconductor chips constituting the second chip block are commonly on the first or second wiring planes.
3. A semiconductor device according to claim 1 , wherein at least one of the semiconductor chips constituting the first and second chip blocks has a penetration hole arranged with a conductor therein.
4. A semiconductor device comprising:
first and second chips blocks supported and connected on one surface of the support semiconductor chip and each including one or a plurality of semiconductor chips having an active surface substantially parallel with the one surface of the support semiconductor chip;
an insulator arrangement between the first and second chip blocks; and
an intralevel wiring arrangement within or on a surface of the insulator, on at least one wiring plane that includes an inactive or active surface of any of the semiconductor chips constituting the first or second chip blocks, the intralevel wiring arrangement including first and second intralevel wirings respectively arranged on first and second wiring planes not in a same plane; and
an interlevel wiring connecting between the first and second intralevel wirings.