Simplifying the layout of printed circuit boards
A method of simplifying the layout of a printed circuit board is disclosed that enables an integrated circuit to modify—after the integrated circuit is manufactured—which pads transport which signals. An integrated circuit in accordance with the illustrative embodiment comprises a two-dimensional array of pads. At the time that the integrated circuit is designed, some or all of the pads are assigned to one or more “transposition groups.” One or more pads are included in a transposition group when, for example, it might be necessary or advantageous to transpose the signals carried by those pads after the integrated circuit has been manufactured. One or more of these transpositions can, for example, greatly simplify the layout of a printed circuit board.
1. An integrated circuit comprising:
a first signal lead;
a second signal lead;
a first pad electrically connected to said first signal lead when said integrated circuit is in a first transposition mode and electrically connected to said second signal lead when said integrated circuit is in a second transposition mode;
a second pad electrically connected to said second signal lead when said integrated circuit is in said first transposition mode and electrically connected to said first signal lead when said integrated circuit is in said second transposition mode; and
a transposing multiplexor for electrically connecting said first signal lead to said first pad and said second signal lead to said second pad when said integrated circuit is in said first transposition mode and for electrically connecting said first signal lead to said second pad and said second signal lead to said first pad when said integrated circuit is in said second transposition mode.
2. An integrated circuit comprising:
an array of pads, P N,M , wherein N and M are positive integers;
an array of signal leads, SL N,M ;
a transposing multiplexor for mapping pad P i,j to signal lead SL i,j when said integrated circuit is in a first transposition mode and for mapping pad P i,j to signal lead SL (N−i+1)j when said integrated circuit is in a second transposition mode;
wherein i is all positive integers less than and including N; and
wherein j is all positive integers less than and including M.
3. The integrated circuit of claim 2 wherein said transposing multiplexor further maps pad P i,j to signal lead SL i,(M−j+1) when said integrated circuit is in a third transposition mode.
4. The integrated circuit of claim 3 wherein said transposing multiplexor further maps pad P i,j to signal lead SL (N−i+1), (M−j+1) when said integrated circuit is in a fourth transposition mode.
5. The integrated circuit of claim 2 wherein said integrated circuit comprises a first transposition group and a second transposition group, and wherein said second transposition group is a non-empty proper subset of said first transposition group.
6. The integrated circuit of claim 2 wherein said integrated circuit comprises a first transposition group, a second transposition group, and a third transposition group, and wherein said second transposition group is a non-empty proper subset of said first transposition group and wherein said third transposition group is a non-empty proper subset of said first transposition group.
7. An integrated circuit comprising:
an array of pads, P, for transporting an array of signal leads, S, wherein N and M are positive integers;
a first transposition group that comprises a non-empty subset of said array of pads and that is characterized by the transposition matrix T 1 ; and
a transposing multiplexor for mapping said array of pads, P, to said array of signal leads, S;
wherein the mapping of said array of pads, P, to said array of signal leads, S, is P⇄S when said integrated circuit is in a first transposition mode; and
wherein the mapping of said array of pads, P, to said array of signal leads, S, is P⇄S∘T 1 when said integrated circuit is in a second transposition mode.
8. The integrated circuit of claim 7 further comprising a second transposition group that comprises a second non-empty proper subset of said first transposition group and that is characterized by the transposition matrix T 2 ;
wherein the mapping of said array of pads, P, to said array of signal leads, S, is P⇄S∘T 2 when said integrated circuit is in a third transposition mode; and
wherein the mapping of said array of pads, P, to said array of signal leads, S, is P=S∘T 1 ∘T 2 when said integrated circuit is in a fourth transposition mode.
9. The integrated circuit of claim 8 further comprising a third transposition group that comprises a third non-empty proper subset of said first transposition group and that is characterized by the transposition matrix T 3 ;
wherein the mapping of said array of pads, P, to said array of signal leads, S, is P=S∘T 3 when said integrated circuit is in a fifth transposition mode.
10. The integrated circuit of claim 9 wherein the mapping of said array of pads, P, to said array of signal leads, S, is P=S∘T 1 ∘T 3 when said integrated circuit is in a sixth transposition mode;
wherein the mapping of said array of pads, P, to said array of signal leads, S, is P=S∘T 2 ∘T 3 when said integrated circuit is in a seventh transposition mode; and
wherein the mapping of said array of pads, P, to said array of signal leads, S, is P=S∘T 1 ∘T 2 ∘T 3 when said integrated circuit is in an eighth transposition mode.
11. The integrated circuit of claim 9 wherein said second transposition group and said third transposition group are mutually exclusive.
12. The integrated circuit of claim 9 wherein said second transposition group and said third transposition group overlap.
13. The integrated circuit of claim 7 wherein said first transposition group comprises a proper subset of said array of pads.
14. The integrated circuit of claim 7 wherein said first transposition group comprises all of said array of pads.