Method and circuit for compensating for tunneling current

1. A circuit comprising:

a tunneling leakage monitor circuit, said tunneling leakage monitor circuit comprising a first PFET, a second PFET, a first NFET and a second NFET, sources of said first and second PFETS connected to a voltage source, gates of said first and second PFETs and said drain of said first PFET connected to a drain of said first NFET, a drain of said second PFET connected to a gate of said second NFET, sources of said first and second NFETs and a drain of said second NFET connected to ground;

a current mirror connected to a gate of said first NFET, said current mirror adapted to force a current of a predetermined value from said gate of said second NFET, through a gate dielectric layer of said second NFET, through said source and said drain of said second NFET to ground, said current consisting of tunneling leakage current;

an input of a voltage buffer connected to said gate of said second NFET, said voltage buffer adapted to generate an output voltage based on a voltage level developed across said gate dielectric layer of said second NFET when said current is at said predetermined current value; and

a voltage regulator coupled to said voltage burner, said voltage regulator adapted to supply a fixed voltage to a power distribution network of an integrated circuit chip based on said output voltage of said voltage buffer.

2. The circuit of claim 1 , wherein said current mirror includes an adjustable current source and means to adjust a current generated by said current source.

3. The circuit of claim 1 , wherein said current source is a band gap current source and said means to adjust said current generated by said current source is a digital to analog converter.

4. The circuit of claim 1 , further including a fuse array, said fuse array adapted to apply input signals to inputs of said digital to analog converter based on a state of fuses in said fuse array or a field programmable gate array, said field programmable gate array adapted to apply input signals to inputs of said digital to analog converter based on a programming of said field programmable gate array.

5. A method of compensating for tunneling current leakage in an integrated circuit chip, the method comprising:

forcing a current of known value only through a dielectric layer of a tunneling current leakage monitor circuit to provide a voltage signal, said tunneling leakage monitor circuit 3 comprising a tunneling leakage monitor circuit, said tunneling leakage monitor circuit comprising first 388 PFET, a second PFET, a first NFET and a second NFET, sources of said first and second PFETS connected to a voltage source, gates of said first and second PFETs and said drain of said first PFET connected to a drain of said first NFET, a drain of said second PFET connected to a gate of said second NFET, sources of said first and second NFETs and a drain of said second NFET connected to ground; and

regulating an on-chip power supply of said integrated circuit chip based on said voltage signal.

6. The method of claim 5 , further including programming fuses or a field programmable gate array in order to set said value of said known current.

7. The method of claim 5 , further including performing a test at a voltage level higher than a normal operating voltage level of said integrated circuit chip while forcing said current of known value through a gate dielectric layer of said second NFET.

8. The method of claim 5 , wherein said current of known value is selected to be about equal to the tunneling leakage current of a worst-ease process integrated circuit chip.

9. The method of claim 5 , further including lowering a voltage level of said on-chip power supply for a best-case process integrated circuit chip from a nominal value for a nominal-case process integrated circuit chip and raising said voltage level of said on-chip power supply for a worst-case process integrated circuit chip from said nominal value.

10. The method of claim 5 , further including:

selecting a first value for said current of known value for burn-in testing of said integrated circuit that is higher than a second value for said current of known value for normal operation of said integrated circuit; and

determining a voltage level of a burn-in test power supply based on said first value.

11. A method of compensating for tunneling current leakage in an integrated circuit chip, the method comprising;

providing a tunneling leakage monitor circuit, said tunneling leakage monitor circuit comprising a first PFET, a second PFET, a first NFET and a second NFET, sources of said first and second PFETS connected to a voltage source, gates of said first and second PFETs and said drain of said first PFET connected to a drain of said first NFET, a drain of said second PFET connected to a gate of said second NFET, sources of said first and second NFETs and a drain of said second NFET connected to ground;

providing a current mirror, said current mirror connected to a gale of said first NFET, said current mirror adapted to force a current of a predetermined value from said gate of said second NFET, through a gate dielectric layer of said second NFET, through said source and said drain of said second NFET to ground, said current consisting of tunneling leakage current;

providing a voltage buffer, an input of said voltage buffer connected to said gate of said second NFET, said voltage buffer adapted to generate an output voltage based on a voltage level developed across said-gate dielectric layer of said second NFET when said current is at said predetermined current value; and

providing a voltage regulator coupled to said voltage buffer, said voltage regulator for supplying a fixed voltage to a power distribution network of an integrated circuit chip based on said output voltage of said voltage buffer.

12. The method of claim 11 , wherein said current mirror includes a current source and a digital to analog converter.

13. The method of claim 11 , further including providing a fuse array, said fuse array for applying input signals to inputs of said digital to analog converter based on a state of fuses in said fuse array or providing a field programmable gate array, said field programmable gate array for applying input signals to inputs of said digital to analog converter based on a programming of said field programmable gate array.

14. The circuit of claim 1 , wherein said voltage buffer comprises a digital amplifier and a third PFET, an output of said digital amplifier connected to a gate of said third PFET, a source of said third PFET connected to said voltage source, a drain of said third PFET connected to an additional input of said digital amplifier and to an output of said voltage buffer.

15. The circuit of claim 1 , further including:

a voltage regulator connected to an output of said voltage buffer; and

a power distribution network of an integrated circuit chip connected to an output of said voltage regulator.

16. The method of claim 11 , wherein said voltage buffer comprises a digital amplifier and a third PFET, an output of said digital amplifier connected to a gate of said third PFET, a source of said third PFET connected to said voltage source, a drain of said third PFET connected to an additional input of said digital amplifier and to an output of said voltage buffer.

17. The method of claim 11 , further including:

providing a voltage regulator connected to an output of said voltage buffer; and

providing a power distribution network of an integrated circuit chip connected to an output of said voltage regulator.