IP Library Granted Patent US 6,987,070
Granted Patent B2
US 6,987,070 · App. 10/874,928 · Granted Jan 17, 2006

Method for forming low-k dielectric layer of semiconductor device

Assignee: Hynix Semiconductor Inc.
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Quick Facts
Patent No.
US 6,987,070
App. No.
10/874,928
Granted
Jan 17, 2006
Kind
B2
Abstract

Disclosed is a method for forming a low-k dielectric layer of a semiconductor device. The method includes a step providing a semiconductor substrate having a predetermined pattern, a step coating porous powders having a micro size on the semiconductor by spraying the porous powders, and a step performing a heat treatment process with respect to a resultant structure, thereby forming the low-k dielectric layer. After micro-sized porous powders are coated on a semiconductor substrate, a heat treatment process is performed, so that powders are bonded to each other, thereby forming a low-k dielectric layer even if the dielectric layer has a dielectric constant equal to or less than 2.8. A signal delay time is reduced by depositing the low-k dielectric layer on the semiconductor substrate.

Claims (10)

1. A method for forming a low-k dielectric layer of a semiconductor device, the method comprising the steps of:

i) providing a semiconductor substrate having a predetermined pattern;

ii) coating micro-sized particles of porous powder on the semiconductor; and

iii) performing a heat treatment process with respect to a resultant structure, wherein the micro-sized particles bond with each other to form the low-k dielectric layer of equal to or less than 2.8 dielectric constant and having a plurality of pores formed therein.

2. The method as claimed in claim 1 , wherein step ii) is performed under an inert gas atmosphere.

3. The method as claimed in claim 1 , wherein the dry porous powder is sprayed onto the while semiconductor substrate is rotating about a non-stationary rotating center when step ii) is performed.

4. The method as claimed in claim 1 , wherein impurities are doped into porous powders having the micro size.

5. The method as claimed in claim 1 , wherein steps ii) and iii) are performed in a same chamber.

6. The method as claimed in claim 1 , further comprising a step of performing a chemical mechanical polishing process with respect to the low-k dielectric layer in order to adjust a thickness of the low-k dielectric layer, after the heat treatment step is performed.

7. The method as claimed in claim 1 , wherein the heat treatment step is carried out by using one of an RTP (rapid thermal process), a high-density plasma process, and a laser heat treatment process.

Assignments (7)
CHANGE OF NAME Recorded Mar 12, 2024
From: KEY FOUNDRY CO., LTD.
To: SK KEYFOUNDRY INC.
Reel/Frame 066794/0290 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2020
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: KEY FOUNDRY CO., LTD.
Reel/Frame 053703/0227 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL: 024563 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY. Recorded Nov 25, 2014
From: US BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 034469/0001 →
RELEASE OF SECURITY INTEREST Recorded Jun 22, 2010
From: U.S. BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 024563/0807 →
AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Recorded Feb 18, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 022277/0133 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2005
From: HYNIX SEMICONDUCTOR, INC.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 016216/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2004
From: MAENG, JONG SUN
To: HYNIX SEMICONDUCTOR, INC.
Reel/Frame 015518/0379 →
Priority Claims (1)
KR 10-2003-0081973 · Nov 19, 2003 · national
Continuity (1)
Related Publication 20050106862A1 · May 19, 2005