IP Library › Granted Patent US 6,992,499
Granted Patent B2
US 6,992,499 · App. 10/859,189 · Granted Jan 31, 2006

Test method and test apparatus for semiconductor device

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 6,992,499
App. No.
10/859,189
Granted
Jan 31, 2006
Kind
B2
Abstract

A method for testing a semiconductor device, is disclosed, which comprises detecting a defect in a semiconductor wafer having a plurality of chips on each of which a plurality of semiconductor elements are formed, to detect those of the chips which have a defect, and carrying out a fist electrical characteristics test to a first chip without defect, and a second electrical characteristics test which is more detailed than the first electrical characteristics test to a second chip having the defect.

Claims (22)

1. A method for testing a semiconductor device, comprising:

detecting a defect in a semiconductor wafer having a plurality of chips on each of which a plurality of semiconductor elements are formed, and detecting chips which have the defect; and

carrying out a first electrical characteristics test to a first chip without the defect, and a second electrical characteristics test, which is more detailed than the first electrical characteristics test, to a second chip having the defect, wherein the second electrical characteristics test has more test parameters than the first electrical characteristics test.

2. A method according to claim 1 , wherein the first electrical characteristics test is carried out to a predetermined ratio of the semiconductor elements in the first chip, and the second electrical characteristics test is carried out to all the elements in the second chip.

3. A method according to claim 2 , wherein the predetermined ratio is 95%.

4. A method according to claim 1 , wherein the defect detection is carried out two or more times in accordance with a semiconductor manufacturing process.

5. A method according to claim 4 , wherein the second electrical characteristics test is carried out to a chip in which the defect is detected in any of the detections.

6. A method according to claim 4 , wherein the first electrical characteristics test is carried out to a chip in which the defect is not detected in any of the detections.

7. A method according to claim 1 , wherein the defect detection is carried out two or more times in accordance with a semiconductor manufacturing process.

8. A method according to claim 7 , wherein the second electrical characteristics test is carried out to a chip in which the defect is detected in any of the detections.

9. A method according to claim 7 , wherein the first electrical characteristics test is carried out to a chip in which the defect is not detected in any of the detections.

10. A test apparatus for use in a process of manufacturing a semiconductor device, comprising:

a detector configured to detect a defect in a semiconductor wafer having a plurality of chips on each of which a plurality of semiconductor elements are formed, and to detect chips which have the defect; and

a test unit configured to carry out a first electrical characteristics test to a first chip without the defect, and a second electrical characteristics test, which is more detailed than the first electrical characteristics test, to a second chip having the defect, wherein the second electrical characteristics test has more test parameters than the first electrical characteristics test.

11. A test apparatus according to claim 10 , wherein the first electrical characteristics test is carried out to a predetermined ratio of the semiconductor elements in the first chip, and the second electrical characteristics test is carried out to all the elements in the second chip.

12. A test apparatus according to claim 11 , wherein the predetermined ratio is 95%.

13. A test apparatus according to claim 11 , wherein the defect detection is carried out two or more times in accordance with a semiconductor manufacturing process.

14. A test apparatus according to claim 13 , wherein the second electrical characteristics test is carried out to a chip in which the defect is detected in any of the detections.

15. A test apparatus according to claim 13 , wherein the first electrical characteristics test is carried out to a chip in which the defect is not detected in any of the detections.

16. A test apparatus according to claim 10 , wherein the defect detection is carried out two or more times in accordance with a semiconductor manufacturing process.

17. A test apparatus according to claim 16 , wherein the second electrical characteristics test is carried out to a chip in which the defect is detected in any of the detections.

18. A test apparatus according to claim 16 , wherein the first electrical characteristics test is carried out to a chip in which the defect is not detected in any of the detections.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2004
From: KUNIHIRO, TAKASHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 015799/0573 →
Priority Claims (1)
JP 2003-159576 · Jun 4, 2003 · national
Continuity (1)
Related Publication 20050009218A1 · Jan 13, 2005