Method for forming inductor in semiconductor device
View Patent ↗The present invention relates to a method for forming an inductor being a passive device in RE MEMS, RFCMOS, Bipolor/SiGe, BiCMOS semiconductor devices. According to the present method, a lower photoresist layer, an intermediate anti-exposure layer and an upper photoresist layer are sequentially formed on a substrate having a lower electrode. The upper photoresist layer is patterned by means of an exposure and development process using a first mask. The exposed intermediate anti-exposure layer is etched until the lower photoresist layer is sufficiently exposed, thus forming a partial via hole. The lower photoresist layer exposed through the upper photoresist layer and the partial via hole are patterned by means of an exposure and development process using a second mask, thus forming a damascene pattern having trenches and a via hole. The damascene pattern is filled with a conductive material layer to form a copper inductor. Not only a thickness of the trenches being line portions and a thickness of the via hole being a contact portion can be uniformly controlled, but also their height can be easily controlled. A high Q inductor can be thus manufactured.
1. A method for forming an inductor in a semiconductor device, comprising the steps of:
forming an inductor formation frame layer in which a lower photoresist layer, an intermediate anti-exposure layer and an upper photoresist layer are sequentially stacked, on a substrate in which a lower electrode is formed;
patterning the upper photoresist layer by means of an exposure and development process using a first mask;
etching the exposed portion of the intermediate anti-exposure layer by means of an etch process using the patterned upper photoresist layer, thus forming a partial via hole;
patterning the lower photoresist layer exposed through the upper photoresist layer and the partial via hole by means of an exposure and development process using a second mask, thereby forming trenches and a via hole; and
filling the trenches and the via hole with an inductor formation material and then stripping the inductor formation frame layer.
2. The method as claimed in claim 1 , wherein the lower photoresist layer is formed in thickness of 1 to 90 μm, the intermediate anti-exposure layer is formed 0.5 to 10 μm in thickness, and the upper photoresist layer is formed in thickness of 1 to 20 μm.
3. The method as claimed in claim 1 , wherein the intermediate anti-exposure layer is formed using oxide, nitride, or a conductive material having a high selective etch ratio against the inductor formation material.
4. The method as claimed in claim 1 , wherein the intermediate anti-exposure layer is formed using a material having at least anti-exposure function and low-temperature deposition property.
5. The method as claimed in claim 1 , wherein the intermediate anti-exposure layer is formed using porous oxide by means of a plasma chemical vapor deposition method at a low temperature of 250° C. or less.
6. The method as claimed in claim 1 , wherein if the intermediate anti-exposure layer is formed using oxide, the process of stripping the inductor formation frame layer is implemented using a diluted wet etch solution containing a HF solution or a BOE solution, a photoresist-stripping solvent, or a mixture of them.
7. The method as claimed in claim 1 , wherein if the intermediate anti-exposure layer is formed using oxide, the process of stripping the inductor formation frame layer comprises the steps of:
stripping the upper photoresist layer using a photoresist-stripping solvent or oxygen plasma;
stripping the intermediate anti-exposure layer using a H 3 PO 4 solution; and
stripping the lower photoresist layer using a photoresist-stripping solvent or oxygen plasma.
8. The method as claimed in claim 1 , further comprising the steps of:
before the lower electrode is formed, forming a metal seed layer on the substrate; and
after the inductor formation frame layer is stripped, stripping the metal seed layer exposed at portions other than the lower electrode.
9. The method as claimed in claim 8 , wherein the metal seed layer is stripped using an acid solution such as H 2 O 2 .