Zirconium oxide and hafnium oxide etching using halogen containing chemicals
View Patent ↗A method is described for selectively etching a high k dielectric layer that is preferably a hafnium or zirconium oxide, silicate, nitride, or oxynitride with a selectivity of greater than 2:1 relative to silicon oxide, polysilicon, or silicon. The plasma etch chemistry is comprised of one or more halogen containing gases such as CF 4 , CHF 3 , CH 2 F 2 , CH 3 F, C 4 F 8 , C 4 F 6 , C 5 F 6 , BCl 3 , Br 2 , HF, HCl, HBr, HI, and NF 3 and leaves no etch residues. An inert gas or an inert gas and oxidant gas may be added to the halogen containing gas. In one embodiment, a high k gate dielectric layer is removed on portions of an active area in a MOS transistor. Alternatively, the high k dielectric layer is used in a capacitor between two conducting layers and is selectively removed from portions of an ILD layer.
1. A method of removing a high k dielectric layer from a substrate, comprising the steps of:
(a) providing a substrate with isolation regions and an active area between said isolation regions;
(b) depositing a high k dielectric layer on said substrate;
(c) forming a patterned gate electrode on said high k dielectric layer; and
(d) anisotropically etching through exposed portion of said high k dielectric layer with a plasma etch comprising one or more halogen containing gases;
wherein said anisotropically etching step is performed in an etch chamber and is comprised of a flow rate between about 2 and 100 standard cubic centimeters per minute (sccm) for the one or more halogen containing gases, at a temperature between 20° C. and 200° C.;
wherein said anisotropically etching step includes of adding one or more O 2 , CO, CO 2 , and N 2 O as an oxidant gas having a flow rate between about 10 and 300 sccm, said oxidant gas including O 2 ; and
wherein said high k dielectric layer includes HfO 2 , wherein said halogen containing gases includes CF 4 and CH 3 F, and wherein said anisotropically etching step includes a CF 4 flow rate of about 30 sccm, a CH 3 F flow rate of about 60 sccm, an O 2 flow rate of about 10 sccm, a 5 mTorr chamber pressure, a RF power of about 600 Watts and a bias power of about 200 Watts for a period of about 10 seconds.
2. The method of claim 1 further comprised of forming an interfacial layer on said substrate prior to depositing said high k dielectric layer.
3. The method of claim 2 wherein the interfacial layer is comprised of silicon oxide, silicon nitride, or silicon oxynitride with a thickness between about 1 and 30 Angstroms.
4. The method of claim 1 wherein said high k dielectric layer has a thickness from about 10 to 120 Angstroms.
5. The method of claim 1 wherein said high k dielectric layer is formed by an atomic layer deposition (ALD), chemical vapor deposition (CVD) or metal organic CVD (MOCVD) technique.
6. The method of claim 1 wherein said high k dielectric layer includes one of Ta 2 O 5 , TiO 2 , Al 2 O 3 , Y 2 O 3 and La 2 O 5 as a minor component.
7. The method of claim 1 wherein said one or more halogen containing gases further includes least one of CHF 3 , CH 2 F 2 , BCl 3 , Br 2 , HF, HCl, HBr, HI, NF 3 .
8. The method of claim 1 wherein said anisotropically etching further includes adding one or more of Ar, Xe, He, and N 2 as a inert gas having a flow rate between about 10 and 250 sccm.
9. The method of claim 1 wherein the substrate is silicon and the isolation regions are comprised of silicon oxide and the etch rate of said high k dielectric layer in step (d) is more than twice the rate of etching silicon oxide or silicon.
10. A method of removing a high k dielectric layer from a substrate, comprising the steps of:
(a) providing a substrate with isolation regions and an active area between said isolation region;
(b) depositing a high k dielectric layer on said substrate;
(c) forming a patterned gate electrode on said high k dielectric layer; and
(d) anisotropically etching through exposed portions of said high k dielectric layer with a plasma etch comprising one or more halogen containing gases;
wherein said anisotropically etching step is performed in an etch chamber and is comprised of a flow rate between about 2 and 100 standard cubic centimeters per minute (sccm) for the one or more halogen containing gases, at a temperature between 20° C. and 200° C. ;
wherein said anisotropically etching step includes adding one or more of Ar, Xc, He, and N 2 as a inert gas having a flow rate between about 10 and 250 sccm said inert gas includes Ar;
wherein said anisotropically etching step includes adding one or more of O 2 , CO, CO 2 , and N 2 O, as an oxidant gas having a flow rate between about 10 and 300 sccm said oxidant gas including O 2 ; and
wherein said high k dielectric layer includes HfO 2 includes a CF 4 flow rate of about 5 sccm, an O 2 flow rate of about 200 sccm, an Ar flow rate of about 100 sccm with a chamber pressure of 20 mTorr, a RF power of about 600 Watts, and a bias power of about 100 Watts for a period of about 23 second to end point plus an overetch period for about an additional 23 seconds beyond end point.
11. A method comprising:
providing a substrate;
depositing a high k dielectric layer above said substrate;
forming a patterned layer above said high k dielectric layer; and
selectively etching exposed portions of said high k dielectric layer with a plasma etch comprising one or more halogen containing gases;
wherein the selectively etching step is performed in an etch chamber and is comprised of a flow rate between about 2 and 100 standard cubic centimeters per minute (sccm) for the one or more halogen containing gases, at a temperature between 20° C. and 200° C.;
wherein said selectively etching includes adding one or more of O 2 , CO, CO 2 , and N 2 O as an oxidant gas having a flow rate between about 10 and 300 sccm said oxidant gas including O 2 ; and
wherein said high k dielectric layer includes HfO 2 wherein said halogen containing gases include CF 4 and CH 3 F, and wherein said selectively etching includes a CF 4 flow rate of about 30 sccm a CH 3 F flow rate of about 60 sccm, an O 2 , flow rate of about 10 sccm, a 5 mTorr chamber pressure, a RF power of about 600 Watts and a bias power of about 200 Watts for a period of about 10 seconds.
12. The method of claim 11 , including:
configuring said substrate to have isolation regions, and an active area between said isolation regions;
configuring said patterned layer to be a patterned gate electrode on said high k dielectric layer; and
carrying out said selectively etching in a manner that includes anisotropically etching through said high k dielectric layer with said plasma etch.
13. The method of claim 11 , including:
configuring said patterned layer to be a patterned photoresist layer;
carrying out said selectively etching in a manner that includes anisotropically etching through said high k dielectric layer with said plasma etch;
removing said photoresist;
etch transferring said pattern in said high k dielectric layer into said substrate; and
removing said high k dielectric layer with a plasma etch comprising a halogen containing gas.
14. The method of claim 11 , including:
providing an interlevel dielectric (ILD) layer over said substrate before said depositing of said high k dielectric layer;
forming in said ILD layer a pattern that includes an opening with sidewalls and a bottom;
forming a first conducting layer on the sidewalls of said opening;
thereafter carrying out said depositing of said high k dielectric layer to form said high k dielectric layer on the first conducting layer;
forming a second conducting layer on maid high k dielectric layer.