Flip chip package structure
A flip chip package structure comprising a chip, a substrate, at least a first bump and a plurality of second bumps is provided. The chip has a first bump-positioning region and the substrate has a second bump-positioning region. The substrate has at least a first hole and multiple second holes. The first hole and the second holes are located within the second bump-positioning region. The first hole has a depth greater than that of the second hole. The first bump is set up between the first bump-positioning region of the chip and the second bump-positioning region of the substrate. The first bump is bonded to the substrate through the first holes. The second bumps are set up between the first bump-positioning region of the chip and the second bump-positioning region of the substrate. The second bumps are bonded to the substrate through the second holes. The first bump has a volume greater than the volume of the second bump.
1. A flip chip package structure, comprising:
a chip having a first bump-positioning region;
a substrate having a second bump-positioning region, at least a first hole and a plurality of second holes, wherein the first hole and the second holes are located within the second bump-positioning region, and the first hole has a depth greater than the second holes;
at least a first bump arranged between the first bump-positioning region of the chip and the second bump-positioning region of the substrate, wherein the first bump and the substrate are bonded together via the first hole;
a plurality of second bumps arranged between the first bump-positioning region of the chip and the second bump-positioning region of the substrate, wherein the second bumps and the substrate are bonded together via the second holes; and
a filler material disposed between the chip and the substrate and encapsulating the first bumps and the second bumps;
wherein the first bump has a volume larger than a volume of the second bump.
2. The flip chip package structure of claim 1 , wherein when there is one first bump and one first hole, the first bump is located in the middle of the first bump-positioning region of the chip and the first hole is located in the middle of the second bump-positioning region.
3. The flip chip package structure of claim 1 , wherein when there are two first bumps and two first holes, the two first bumps are positioned between the chip and the substrate and symmetrical relative to a centroid of the first bump-positioning region, and the two first holes are positioned in the second bump-positioning region and symmetrical relative to a centroid of the second bump-positioning region.
4. The flip chip package structure of claim 1 , wherein the package structure has a plurality of first bumps and the first bumps are located close to corners of the first bump-positioning region and located between the chip and the substrate, and the substrate has a plurality of first holes and the first holes are positioned close to corners of the second bump-positioning region.
5. The flip chip package structure of claim 1 , wherein the first bump arranged between the chip and the substrate physically but not electrically connects the chip and the substrate.
6. The flip chip package structure of claim 1 , wherein the first bump arranged between the chip and the substrate electrically and physically connects the chip and the substrate.
7. The flip chip package structure of claim 1 , wherein the first bump further comprises:
a conductive pillar arranged on the chip; and
a soldering block arranged on the conductive pillar.
8. The flip chip package structure of claim 1 , wherein the first bump has a height ranging from about 150 μm to about 200 μm.