Ramped soft programming for control of erase voltage distributions in flash memory devices
View Patent ↗A method of erasing bits in a multi-level cell flash memory array is described. The method includes applying over-erase verification after each erase pulse. If cells verify as over-erased, a ramped over-erase correction pulse is applied. The voltage of each over-erase correction pulse is incrementally greater than the previous pulse, until all bits in all cells pass the over-erase verification. In this way, the widths of the threshold voltage distributions of the erased bits are kept to a minimum.
1. A method for performing over-erase correction after erase in a flash Electrically-Erasable Programmable Read Only Memory (EEPROM) that includes a plurality of field-effect transistor memory cells each having a source, a drain, a bitline connected to said drain, a floating gate, a well and a control gate, the method comprising:
(a) applying an overerase verify pulse after each erase pulse in the erase process to determine if one of the flash memory cells is overerased;
(b) applying an overerase correction pulse after each determining step indicates an overerased cell exists;
(c) applying an overerase verify pulse after each overerase correction pulse, and if one of the flash memory cells is overerased, applying an incremented overerase correction pulse;
(d) incrementing the voltage of each successive overerase correction pulse by ΔV; and
(e) repeating (a)–(d) until none of said plurality of cells verifies as over-erased.
2. The method of claim 1 , wherein over-erased cells are detected by the presence of a bitline leakage current.
3. The method of claim 1 , wherein (c) is accomplished by applying a ramped voltage to the bitline.
4. The method of claim 1 , wherein (c) is accomplished by applying a stepped voltage to the bitline.
5. The method of claim 1 , wherein (c) is accomplished by applying an increasing positive voltage.
6. The method of claim 1 , wherein the voltage to the bitline is increased in equal increments.
7. The method of claim 1 , wherein the voltage to the bitline is increased in unequal increments.
8. The method of claim 1 , wherein the complete correction of over-erased cells is determined by the absence of a bitline leakage current.
9. The method of claim 1 , wherein each over-erase correction pulse is applied for a duration of 10–100 micro seconds.
10. The method of claim 1 , wherein each cell is verified for over-erase after each over-erase correction pulse is applied.
11. A multi-level flash Electrically Erasable Programmable Read Only Memory (EEPROM) device that includes a plurality of field-effect transistor memory cells each having a source, a drain, a bitline connected to said drain, a floating gate, a well and a control gate comprising:
a means for programming each level of each cell;
a means for reading each level of each cell;
a means for erasing each level of each cell;
a means for verifying each level of each cell for undererase;
a means for correcting any undererased cells;
a means for verifying each level of each cell for over-erase; and
a means for correcting any over-erased cells by using an incremented voltage applied to the bitline.
12. The apparatus of claim 11 , wherein the over-erase correction voltage to the bitline is ramped.
13. The apparatus of claim 11 , wherein the over-erase correction voltage to the bitline is stepped.
14. The apparatus of claim 11 , wherein the over-erase correction voltage to the bitline is incremented by applying an increasingly positive voltage.
15. The apparatus of claim 11 , wherein the over-erase correction voltage to the bitline is increased in equal increments.
16. The apparatus of claim 11 , wherein the over-erase correction voltage to the bitline is increased in unequal increments.