Method for manufacturing dual damascene structure with a trench formed first
View Patent ↗A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer are subsequently formed thereon. A trench is formed in the dielectric layer at a predetermined depth thereafter, and a sacrificial layer is filled therein and is next planarized. Then a photoresist layer is formed thereon for etching a via. Afterward the photoresist layer and the sacrificial layer are both removed. Following that, the first etching stop layer is etched through to expose the first metal layer. Finally, the via and the trench are filled with a second metal layer.
1. A method for manufacturing dual damascene structure with a trench formed first, comprising the steps of:
providing a substrate having a plurality of semiconductor devices;
forming a first metal layer on the substrate;
forming a first etching stop layer on the first metal layer;
forming a dielectric layer on the first etching stop layer;
forming a second etching stop layer on the dielectric layer;
forming a first patterned photoresist layer on the second etching stop layer;
forming a trench by etching though the second etching stop layer and stopping in the dielectric layer at a predetermined depth;
filling with a sacrificial layer into the trench;
planarizing the sacrificial layer;
forming a second patterned photoresist layer on the sacrificial layer;
forming a via by etching the sacrificial layer and the dielectric layer;
removing the sacrificial layer and the second patterned photoresist layer;
etching the first etching stop layer to expose the first metal layer;
filling with a second metal layer; and
planarizing the second metal layer.
2. The method of claim 1 , wherein the first metal layer comprises copper.
3. The method of claim 1 , wherein the second metal layer comprises copper.
4. The method of claim 1 , wherein the dielectric layer is made of a material selected from a group consisting of fluorinated silicate glass (FSG), silicon dioxide, black diamond (BD), SiLK, CORAL, methyl silsesquioxane (MSQ), and hydrogen silsesquioxane (HSQ).
5. The method of claim 1 , wherein the dielectric layer has a dielectric constant of about 1.0 to about 4.0.
6. The method of claim 1 , wherein the predetermined depth is less than a thickness of the dielectric layer.
7. The method of claim 1 , wherein the sacrificial layer is 0.5–1.5 times a thickness of the dielectric layer.
8. The method of claim 1 , wherein an etching rate ratio of the sacrificial layer to the dielectric layer is about 0.7:1 to 1.3:1.
9. The method of claim 1 , wherein the step of forming a via by etching the sacrificial layer and the dielectric layer is stopped at the first etching stop layer.
10. The method of claim 1 , further comprising the step of:
forming a third etching stop layer on the second metal layer for subsequent processes.
11. The method of claim 1 , wherein the second patterned photoresist layer and the dielectric layer are separated by the sacrificial layer and the second etching stop layer.
12. The method of claim 1 , wherein the first etching stop layer comprises a diffusion-barrier layer.
13. The method of claim 1 , wherein the second etching stop layer comprises a hard mask layer.
14. The method of claim 1 , wherein the second etching stop layer comprises an anti-reflection layer.