Interconnection structure of semiconductor device
An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.
1. An interconnection structure of a semiconductor device having a dummy interconnection electrically connected to an interconnection forming a portion of a circuit, said dummy interconnection provided with a stress concentration portion having tensile stress higher than that of said interconnection generated therein, and
wherein the tensile stress in said stress concentration portion is not less than 200 MPa nor more than 400 Mpa.
2. The interconnection structure of a semiconductor device according to claim 1 , wherein said dummy interconnection has a first end portion and a second end portion, said first end portion electrically connected to said interconnection and said second end portion electrically disconnected.
3. The interconnection structure of a semiconductor device according to claim 2 , wherein said dummy interconnection is formed of a via.
4. The interconnection structure of a semiconductor device according to claim 1 , wherein the tensile stress is generated in said stress concentration portion by providing an insulating film having internal stress of compression, in proximity to said stress concentration portion or in contact with said stress concentration portion.
5. The interconnection structure of a semiconductor device according to claim 4 , wherein said insulating film is a SiN film deposited by plasma CVD.