IP Library › Granted Patent US 7,172,972
Granted Patent B2
US 7,172,972 · App. 10/883,828 · Granted Feb 6, 2007

Semiconductor device manufacture method and etching system

Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 7,172,972
App. No.
10/883,828
Granted
Feb 6, 2007
Kind
B2
Abstract

A semiconductor device manufacture method includes the steps of forming a resist layer above a work target layer; exposing and developing the resist layer to form resist patterns including isolated pattern and dense patterns; monitoring widths of isolated and dense pattern of the resist patterns to determine trimming amounts of linewidths to be reduced; determining etching conditions for realizing the trimming amounts of both the isolated and dense patterns, the etching conditions using mixed gas of a gas having a function of mainly enhancing etching and a gas having a function of mainly suppressing etching; trimming the resist pattern under said determined etching conditions; and etching the work target layer by using said trimmed resist patterns. A desired pattern width an be realized stably by trimming using plasma etching.

Claims (32)

1. A semiconductor device manufacture method comprising steps of:

(a) preparing a semiconductor substrate having a work target layer;

(b) forming a resist layer above said work target layer;

(c) exposing and developing said resist layer to form resist patterns including an isolated pattern and a dense pattern;

(d) monitoring widths of isolated pattern and dense pattern of said resist patterns to determine trimming amounts of widths to be reduced;

(e) determining etching conditions realizing said trimming amounts of both the isolated and dense patterns, the etching conditions using mixed gas comprising a first gas having a function of mainly enhancing etching and a second gas having a function of mainly suppressing etching;

(f) trimming said resist patterns under said determined etching conditions; and

(g) etching said work target layer by using said trimmed resist patterns

wherein the etching conditions in said step (e) use at least one of etching time period and mixing ratio of the mixed gas as a variable.

2. The semiconductor device manufacture method according to claim 1 , wherein said step (e) executes etching process under first etching conditions for part of a plurality of semiconductor devices, measures the trimming amounts, and corrects the first etching conditions by considering the measurement results to obtain second etching conditions for realizing said trimming amounts.

3. The semiconductor device manufacture method according to claim 1 , wherein said step (b) laminates a BARC layer and said resist layer, said step (e) determines the etching conditions of main-etching and thereafter over-etching said BARC layer and trimming said resist layer, and said step (f) etches said BARC layer and trims said resist layer.

4. The semiconductor device manufacture method according to claim 3 , wherein the first gas having the function of mainly enhancing etching is O 2 gas and the second gas having the function of mainly suppressing etching is SO 2 gas.

5. The semiconductor device manufacture method according to claim 3 , wherein the etching conditions in said step (e) include a constant over etching time and a gas-flow-rate fraction at which the trimming amounts of the isolated and dense patterns become substantially equal.

6. The semiconductor device manufacture method according to claim 1 , wherein said work target layer is a polysilicon layer for forming gate electrodes.

7. The semiconductor device manufacture method according to claim 6 , wherein said work target layer further includes a hard mask layer formed on said polysilicon layer.

8. The semiconductor device manufacture method according to claim 1 , wherein said step (c) forms the isolated pattern and the dense pattern having a different linewidth from a linewidth of the isolated pattern, said step (d) determines different trimming amounts for the isolated and dense patterns, and said step (e) determines also etching conditions of auxiliary etching which does not hardly change the pattern linewidth of one of the isolated and dense patterns and reduces the pattern linewidth of the other, and the semiconductor device manufacture method further comprises:

(h) auxiliary-etching said resist pattern.

9. The semiconductor device manufacture method according to claim 8 , wherein said step (h) is executed in He atmosphere.

10. The semiconductor device manufacture method according to claim 1 , wherein said mixed gas further comprises a third gas not chemically reacting with said work target layer.

11. The semiconductor device manufacture method according to claim 10 , wherein the etching conditions in said step (e) uses as a variable at least one of etching time period, a first mixture ratio of the first gas and the second gas, a second mixture ratio of the third gas to, the first and the second gases, and total flow rate of said mixed gas.

12. The semiconductor device manufacture method according to claim 11 , wherein said step (e) uses said first mixture ratio and said second mixture ratio as parameters and determines the etching conditions realizing said trimming amounts of both the isolated and dense patterns.

13. The semiconductor device manufacture method according to claim 12 , wherein said step (e) uses equations expressing the trimming amounts of the isolated and dense patterns as linear functions of said first mixture ratio and said second mixture ratio.

14. The semiconductor device manufacture method according to claim 13 , wherein said step (e) performs correction considering errors caused by using the equations of linear function.

15. An etching system comprising:

a measuring apparatus capable of measuring a pattern linewidth;

an etching apparatus capable controlled trimming of a resist pattern comprising both isolated and dense pattern line widths by using mixed gas of a gas having a function of mainly enhancing etching and a gas having a function of mainly suppressing etching, and thereafter etching a work target layer under the resist pattern; and

a controller for storing data representative of relation between isolated and dense pattern linewidths of the resist pattern, and isolated and dense pattern widths of the work target layer after etching, the relation depending upon etching conditions of the etching using the mixed gas, and etching conditions capable of realizing desired trimming amounts of the isolated and the dense pattern linewidths from given resist pattern,

wherein said measuring apparatus has a feed forward system of measuring the pattern linewidth of the resist pattern and transfer the measurement results to said controller, and said controller determines the etching conditions in accordance with the transferred resist pattern linewidth and controls said etching apparatus.

16. The etching system according to claim 15 , wherein said measuring apparatus includes a feedback system of measuring pattern linewidth after etching and transferring the measurement results to said controller, and said controller corrects data in accordance with the feed-back value.

17. The etching system according to claim 15 , wherein said measuring apparatus further includes a feedback system of measuring a pattern linewidth of the work target layer after etching and transferring the measurement results to said controller, and said controller calculates the trimming amounts from resist pattern width of a pilot wafer and a pattern width of the work target layer of the pilot wafer after etching, calculates change amounts through comparison between the calculation results and said data, and determines etching conditions corrected by said etching conditions and said change amounts to control said etching apparatus.

18. The etching system according to claim 15 , wherein the etching conditions determined by said controller are over etching time and mixing ratio the mixed gas for realizing different trimming amounts for the isolated and dense patterns respectively in a first mode, and are mixing ratio of the mixed gas for realizing substantially same trimming amount for the isolated and dense patterns in a second mode.

19. The etching system according to claim 18 , wherein the etching conditions determined by said controller further include etching conditions substantially trimming only one of the isolated and dense patterns.

Assignments (6)
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 6, 2004
From: GOTO, TAKESHI; TAJIMA, MITSUGU; YAMAZAKI, TAKAYUKI; KATO, TAKAYA
To: FUJITSU LIMITED
Reel/Frame 015549/0483 →
Priority Claims (2)
JP 2003-194380 · Jul 9, 2003 · national
JP 2004-158165 · May 27, 2004 · national
Continuity (1)
Related Publication 20050009215A1 · Jan 13, 2005