Reduced barrier photodiode/transfer gate device structure of high efficiency charge transfer and reduced lag and method of formation
A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the same are disclosed. Embodiments of the invention provide a pixel cell comprising a substrate. A gate of a transistor is formed at least partially below the surface of the substrate and a photodiode is adjacent to the gate. The photodiode comprises a doped surface layer of a first conductivity type, and a doped region of a second conductivity type underlying the doped surface layer. The doped surface layer is at least partially above a level of the bottom of the gate.
1. A pixel cell comprising:
a substrate;
a gate of a transistor formed at least partially below a surface of the substrate, the gate having a bottom surface below the surface of the substrate;
a channel region of the transistor located below the bottom surface of the gate; and
a photo-conversion device formed adjacent to the gate, the photo-conversion device comprising a doped surface layer of a first conductivity type, and a doped region of a second conductivity type underlying the doped surface layer, wherein the doped surface layer is at a level approximately between a level of a top surface of the gate and a level of the bottom surface of the gate, and wherein the second conductivity type layer is at a level below the level of the bottom surface of the gate.
2. The pixel cell of claim 1 , wherein the first and second conductivity types are p and n respectively.
3. The pixel cell of claim 1 , wherein the photo-conversion device is a pinned photodiode.
4. The pixel cell of claim 1 , wherein the gate is the gate of a transfer transistor.
5. The pixel cell of claim 1 , wherein the gate is the gate of a reset transistor.
6. The pixel cell of claim 1 , wherein the gate is the gate of a charge coupled device.
7. The pixel cell of claim 1 , further comprising a sensing node adjacent to the gate and on an opposite side of the gate from the photo-conversion device.
8. The pixel cell of claim 7 , wherein the sensing node is a floating diffusion region.
9. The pixel cell of claim 1 , wherein the doped surface layer has a thickness within the range of approximately 200 to approximately 2000 Å.
10. The pixel cell of claim 1 , wherein the implant dose of a dopant for the doped surface layer is within the range of approximately 1×10 12 to approximately 3×10 14 atoms per cm 2 .
11. The pixel cell of claim 1 , further comprising a trench in the substrate, wherein the gate is at least partially in the trench.
12. The pixel cell of claim 11 , wherein the trench has a depth within the range of approximately 500 to approximately 2500 Å.
13. The pixel cell of claim 1 , wherein the gate comprises:
a conductive layer; and
insulating material, wherein the insulating material is on at least two lateral sides of the conductive layer.
14. The pixel cell of claim 13 , wherein the insulating material on the two lateral sides of the gate has a thickness within the range of approximately 20 to approximately 100 Å thick.
15. The pixel cell of claim 13 , wherein the doped surface layer is in contact with the insulating material.
16. The pixel cell of claim 1 , wherein operation of the gate affects the doped surface layer at least partially through a sidewall of the gate.
17. The pixel cell of claim 1 , wherein the gate is part of a CMOS imager.
18. The pixel cell of claim 1 , wherein the gate is part of a charge coupled device imager.
19. A pixel cell comprising:
a substrate;
a trench in the substrate;
a gate of a transistor at least partially in the trench;
a channel region of the transistor formed below the trench;
a photo-conversion device formed adjacent to the trench, the photo-conversion device comprising a doped surface layer of a first conductivity type below the surface of the substrate, and a doped region of a second conductivity type underlying the doped surface layer of a first conductivity type, wherein the doped surface layer is at least partially above a level of a bottom surface of the trench, wherein the doped surface layer is at a level approximately between a level of a top surface of the gate and a level of the bottom surface of the gate, and wherein the second conductivity type layer is at a level below the level of the bottom surface of the gate.
20. The pixel cell of claim 19 , wherein the trench has a depth within the range of approximately 500 to approximately 2500 Å.
21. The pixel cell of claim 19 , wherein the gate comprises:
a conductive layer; and
insulating material, wherein the insulating material is on at least two lateral sides of the conductive layer.
22. The pixel cell of claim 21 , wherein the insulating material on the two lateral sides of the gate has a thickness within the range of approximately 20 to approximately 100 Å thick.
23. An imager system, comprising:
a processor; and
an imager coupled to the processor, the imager comprising:
a substrate;
a pixel formed over the substrate, the pixel comprising:
a gate of a transistor formed at least partially below a surface of the substrate, the gate having a bottom surface below the surface of the substrate;
a channel region of the transistor located below the bottom surface of the gate; and
a photo-conversion device formed adjacent to the gate, the photo-conversion device comprising a doped surface layer of a first conductivity type, and a doped region of a second conductivity type underlying the doped surface layer, wherein the doped surface layer is at least partially above a level of a bottom surface of the gate wherein the doped surface layer is at a level approximately between a level of a top surface of the gate and a level of the bottom surface of the gate, and wherein the second conductivity type layer is at a level below the level of the bottom surface of the gate.
24. The system of claim 23 , wherein the imager is a CMOS imager.
25. The system of claim 23 , wherein the imager is a charge coupled device imager.
26. The system of claim 23 , wherein the first and second conductivity types are p and n respectively.
27. The system of claim 23 , wherein the photo-conversion device is a pinned photodiode.
28. The system of claim 23 , wherein the gate is the gate of a transfer transistor.
29. The system of claim 23 , wherein the gate is a transfer gate of a charge coupled device.
30. The system of claim 23 , further comprising a sensing node adjacent to the gate and on an opposite side of the gate from the photo-conversion device.
31. The system of claim 23 , wherein the sensing node is a floating diffusion region.
32. The system of claim 23 , wherein the doped surface layer has a thickness within the range of approximately 200 to approximately 2000 Å.
33. The system of claim 23 , further comprising a trench formed in the substrate, wherein the gate is at least partially in the trench.
34. The system of claim 33 , wherein the trench has a depth within the range of approximately 500 to approximately 2500 Å.
35. The system of claim 23 , wherein operation of the gate affects the doped surface layer at least partially through a sidewall of the gate.
36. A pixel cell comprising:
a substrate;
a trench in the substrate;
a gate of a transistor formed in the trench and contained within the lateral boundaries of the trench, the gate having a bottom surface below the surface of the substrate;
a channel region of the transistor located below the bottom surface of the gate; and
a photo-conversion device formed adjacent to the gate, the photo-conversion device comprising a doped surface layer of a first conductivity type, and a doped region of a second conductivity type underlying the doped surface layer, wherein the doped surface layer is at least partially above a level of a bottom surface of the gate and wherein the second conductivity type layer is at a level below the level of the bottom surface of the gate.
37. The pixel cell of claim 36 , wherein the photo-conversion device is a pinned photodiode.
38. The pixel cell of claim 36 , wherein the gate is the gate of a transfer transistor.
39. The pixel cell of claim 36 , wherein the gate is the gate of a reset transistor.
40. The pixel cell of claim 36 , further comprising a sensing node adjacent to the gate and on an opposite side of the gate from the photo-conversion device.
41. The pixel cell of claim 36 , wherein the doped surface layer is at a level approximately between a level of a top surface of the gate and a level of the bottom surface of the gate.
42. The pixel cell of claim 36 , wherein the trench has a depth within the range of approximately 500 to approximately 2500 Å.