Method of forming fully-depleted (FD) SOI MOSFET access transistor
A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.
1. A method of forming a semiconductor device comprising the acts of:
providing a SOI substrate;
forming at least one isolation region in said SOI substrate for separating at least one periphery region of said SOI substrate from at least one memory array region of said SOI substrate;
forming at least one partially-depleted SOI NMOSFET device in said periphery region of said SOI substrate; and
forming at least one fully-depleted SOI NMOSFET device in said memory array region of said SOI substrate, said fully-depleted SOI NMOSFET device comprising a silicon/germanium gate electrode of p-type conductivity.
2. The method of claim 1 , wherein said gate electrode of said fully-depleted SOI MOSFET device is formed of a silicon/germanium layer provided over said memory array region.
3. The method of claim 2 further comprising the act of subjecting said silicon/germanium layer to a first implantation with a p-type dopant.
4. The method of claim 3 , wherein said first implantation is conducted at an energy of about 1 keV to about 50 keV.
5. The method of claim 4 , wherein said first implantation is further conducted at a dose concentration of about 1×10 14 /cm 2 to about 5×10 15 /cm 2 .
6. The method of claim 2 further comprising the act of providing an oxide layer on said memory array region of said SOI substrate before said act of providing said silicon/germanium layer.
7. The method of claim 6 further comprising the act of providing a silicide layer over said silicon/germanium layer.
8. The method of claim 7 further comprising the act of providing a dielectric cap layer over said silicide layer.
9. The method of claim 8 , wherein said act of forming said fully-depleted SOI NMOSFET device further includes the act of patterning said silicon/germanium layer, said silicide layer and said dielectric cap layer formed over said memory array region.
10. The method of claim 9 , wherein said act of forming said fully-depleted SOI NMOSFET device further includes the act of etching said silicon/germanium layer, said silicide layer and said dielectric cap layer to form a gate stack.
11. The method of claim 10 further comprising the act of forming source and drain regions on opposite sides of said gate stack and in said memory array region.
12. The method of claim 11 , wherein said act of forming source and drain regions further comprises the act of subjecting said gate stack to a second implantation with an n-type dopant.
13. The method of claim 12 , wherein said second implantation is conducted at an energy of about 1 keV to about 60 keV.
14. The method of claim 13 , wherein said second implantation is further conducted at a dose concentration of about 1×10 14 /cm 2 to about 5×10 15 /cm 2 .