Substrate for producing semiconductor packages
A parent or master substrate for a semiconductor package is provided, which can provide a plurality of unit substrates by cutting into pieces for producing a semiconductor device. The parent substrate includes an insulation layer, conductor patterns formed on first and second surfaces of the insulation layer, and PSR (photo solder resist) layers respectively formed on the first and second surfaces of the insulation layers and covering the conductor patterns. The parent substrate includes an upper part and a lower part divided by a reference surface which passes through the center of the insulation layer. When an equivalent thermal expansion coefficient α upper of the upper part is defined by the Equation of α upper = ∑ i = 1 n α i × E i × v i ∑ i = 1 n E i × v i , where α i is respective thermal expansion coefficients of, E i is respective elastic moduli of, and v i is respective volume ratios of first through n th components constituting the upper part (e.g., insulation layer, conductor patterns, and PSR layers of the upper part), and an equivalent thermal expansion coefficient α lower of the lower part is defined by the Equation of α lower = ∑ j = 1 m α j × E j × v j ∑ j = 1 m E j × v j , where α j is respective thermal expansion coefficients of, E j is respective elastic moduli of, and v j is respective volume ratios of first through m th components constituting the lower part (e.g., insulation layer, conductor patterns, and PSR layers of the lower part), a equivalent thermal expansion ratio (α upper /α lower ) of α upper to α lower is selected to be within a range of 0.975 through 1.165.
1. A parent substrate for producing a plurality of unit substrates for a semiconductor device, the parent substrate comprising:
an insulation layer having first and second surfaces opposing to each other;
upper and lower conductor patterns respectively formed on the first and second surfaces of the insulation layer; and
upper and lower photo solder resist (PSR) layers respectively formed over the first and second surfaces of the insulation layers and covering at least some area of the upper and lower conductor patterns,
wherein the parent substrate defines an upper part and a lower part divided by a reference surface passing through the center line of the insulation layer,
wherein, when an equivalent thermal expansion coefficient α upper of the upper part is defined as follows:
α
upper
=
α
b
E
b
v
b
+
α
c
E
c
v
c
+
α
p
E
p
v
p
E
b
v
b
+
E
c
v
c
+
E
p
v
p
where α b , α c and α p are thermal expansion coefficients of upper insulation layer, upper conductor pattern and upper PSR layer, respectively, E b , E c and E p are elastic moduli of upper insulation layer, upper conductor pattern and upper PSR layer, respectively, and v b , v c and v p are volume ratios of upper insulation layer, upper conductor pattern and upper PSR layer, respectively, and when an equivalent thermal expansion coefficient α lower of the lower part is defined as follows:
α
lower
=
α
b
E
b
v
b
+
α
c
E
c
v
c
+
α
p
E
p
v
p
E
b
v
b
+
E
c
v
c
+
E
p
v
p
where α b , α c and α p are thermal expansion coefficients of lower insulation layer, lower conductor pattern and lower PSR layer, respectively, E b , E c and E p are elastic moduli of lower insulation layer, lower conductor pattern and lower PSR layer, respectively, and v b , v c and v p are volume ratios of lower insulation layer, lower conductor pattern and lower PSR layer, respectively, an equivalent thermal expansion coefficient ratio (α upper /α lower ) of α upper to α lower is selected to be within a range of between 0.975 and 1.165.
2. The parent substrate of claim 1 , wherein the α upper /α lower is selected to be within a range of between 0.99 and 1.09.
3. The parent substrate of claim 1 , wherein the upper and lower conductor patterns are formed of copper (Cu) and the insulation layer is formed of a FR-4 or BT resin.
4. The parent substrate of claim 1 , wherein the upper conductor patterns formed on the first surface of the insulation layer include an array of circuit patterns for unit substrates disposed at a central area of the parent substrate for transmitting electrical signals there-through, and an array of dummy patterns disposed at a peripheral area of the parent substrate.
5. The parent substrate of claim 4 , wherein the upper and lower PSR layers are respectively covers the entire surface of the upper and lower conductor patterns with the exception of certain areas on the circuit patterns.
6. The parent substrate of claim 1 , wherein the lower conductor patterns formed on the second surface of the insulation layer are an array of dummy patterns not transmitting an electrical signal.
7. A unit substrate formed by cutting out of a parent substrate for providing a semiconductor package, the parent substrate comprising:
an insulation layer having first and second surfaces opposing to each other;
upper and lower conductor patterns respectively formed on the first and second surfaces of the insulation layer; and
upper and lower photo solder resist (PSR) layers respectively formed over the first and second surfaces of the insulation layers and covering at least some area of the upper and lower conductor patterns,
wherein the parent substrate defines an upper part and a lower part divided by a reference surface passing through the center line of the insulation layer,
wherein, when an equivalent thermal expansion coefficient α upper of the upper part is defined as follows:
α
upper
=
α
b
E
b
v
b
+
α
c
E
c
v
c
+
α
p
E
p
v
p
E
b
v
b
+
E
c
v
c
+
E
p
v
p
where α b , α c and α p are thermal expansion coefficients of upper insulation layer, upper conductor pattern and upper PSR layer, respectively, E b , E c and E p are elastic moduli of upper insulation layer, upper conductor pattern and upper PSR layer, respectively, and v b , v c and v p are volume ratios of upper insulation layer, upper conductor pattern and upper PSR layer, respectively, and when an equivalent thermal expansion coefficient α lower of the lower part is defined as follows:
α
lower
=
α
b
E
b
v
b
+
α
c
E
c
v
c
+
α
p
E
p
v
p
E
b
v
b
+
E
c
v
c
+
E
p
v
p
where α b , α c and α p are thermal expansion coefficients of lower insulation layer, lower conductor pattern and lower PSR layer, respectively, E b , E c and E p are elastic moduli of lower insulation layer, lower conductor pattern and lower PSR layer, respectively, and v b , v c and v p are volume ratios of lower insulation layer, lower conductor pattern and lower PSR layer, respectively, an equivalent thermal expansion coefficient ratio (α upper /α lower ) of α upper to α lower is selected to be within a range of between 0.975 and 1.165.
8. The unit substrate of claim 7 , wherein the α upper /α lower is selected to be within a range of between 0.99 and 1.09.