High speed memory system
View Patent ↗A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, precharging of the DRAM array is transparent to the CPU bus.
1. A high speed memory system comprising:
a dynamic random access memory (DRAM); and
a memory control sequencer for accessing the DRAM, wherein the memory control sequencer generates a row access signal and a column access signal for controlling the memory operations of the DRAM in response to at least an external access signal and a clock signal;
wherein the memory control sequencer comprises circuitry for detecting the reception of the external access signal during a first clock phase of the clock signal, asserting the row access signal during the first clock phase, asserting the column access signal during a second clock phase of the clock signal, completing a memory access of the DRAM associated with asserting the row access signal and the column access signal during a third clock phase of the clock signal, and precharging the DRAM during the third clock phase of the clock signal.
2. The memory system of claim 1 , wherein the first clock phase and the second clock phase combined have a duration less than one cycle of the clock signal.
3. The memory system of claim 1 , wherein the second clock phase is less than one clock cycle after the start of the first clock phase.
4. The memory system of claim 1 , wherein the third clock phase is less than one clock cycle after the start of the second clock phase.
5. The memory system of claim 1 , further comprising:
a row address register configured to latch a row address used to access a row of the DRAM;
a column address register configured to latch a column address used to access a column of the DRAM; and
a control circuit that causes the row address to be latched in the row address register before the column address is latched in the column address register.
6. A method of operating a memory array, the method comprising the acts of:
initiating a read access to the memory array during a first clock phase;
reading a first set of data values from the memory array during a second clock phase;
storing the first set of data values read from the memory array in a first data storage circuit during the second clock phase;
isolating the first data storage circuit from the memory array during a third clock phase;
reading the first set of data values from the first data storage circuit during the third clock phase; and
precharging the memory array during the third clock phase.
7. The method of claim 6 , further comprising the acts of:
performing a row access operation on the memory array during the first clock phase;
performing a column access operation on the memory array during the second clock phase, thereby reading the first set of data values from the memory array.
8. The method of claim 6 , wherein the first clock phase and the second clock phase combined have a duration less than one cycle of a clock signal used to read the first set of data values from the first data storage circuit.
9. The method of claim 6 , wherein the second clock phase is less than one clock cycle after the start of the first clock phase.
10. The method of claim 6 , wherein the third clock phase is less than one clock cycle after the start of the second clock phase.
11. The method of claim 6 , further comprising:
latching a row address associated with the read access during the first clock phase; and
latching a column address associated with the read access after latching the row address.