Transistor having vertical junction edge and method of manufacturing the same
Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a heavily doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the heavily doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.
1. A transistor comprising:
a drain terminal comprising a doped polysilicon material disposed within a first shallow cavity formed in an isolation oxide region;
a source terminal comprising a polysilicon material disposed within a second shallow cavity formed in the isolation oxide region;
a channel formed in a silicon material and arranged between each of the first shallow cavity and the second shallow cavity, wherein the channel comprises a respective doped region coupled to each of the drain terminal and the source terminal; and
a gate disposed over the channel and comprising one or more conductive layers disposed over a gate oxide layer.
2. The transistor, as set forth in claim 1 , wherein each of the plurality of cavities comprises a depth in the range of approximately 300 angstroms to 1500 angstroms.
3. The transistor, as set forth in claim 1 , wherein each of the plurality of cavities comprises an aspect ratio of less than or equal to approximately 0.5 to 10.
4. The transistor, as set forth in claim 1 , wherein each of the plurality of cavities comprises an aspect ratio of less than or equal to approximately 1 to 3.
5. The transistor, as set forth in claim 1 , comprising:
a first conductive post coupled to the drain terminal and extending vertically therefrom; and
a second conductive post coupled to the source terminal and extending vertically therefrom;
wherein each of the first and second conductive posts are coupled to the respective drain and source terminals at a distance from the gate that is greater than 50% of the width of the respective drain and source terminals.
6. A memory device comprising:
a storage device; and
a transistor coupled to the storage device, wherein the transistor comprises:
a drain terminal comprising a doped polysilicon material disposed within a first shallow cavity formed in an isolation oxide region;
a source terminal comprising a polysilicon material disposed within a second shallow cavity formed in the isolation oxide region;
a channel formed in a silicon material and arranged between each of the first shallow cavity and the second shallow cavity, wherein the channel comprises a respective doped region coupled to each of the drain terminal and the source terminal; and
a gate disposed over the channel and comprising one or more conductive layers disposed over a gate oxide layer.
7. The memory device, as set forth in claim 6 , wherein the storage device comprises a capacitor.
8. The memory device, as set forth in claim 6 , wherein each of the plurality of cavities comprises a depth in the range of approximately 300 angstroms to 1500 angstroms.
9. The memory device, as set forth in claim 6 , wherein each of the plurality of cavities comprises an aspect ratio of less than or equal to approximately 0.5 to 10.
10. The memory device, as set forth in claim 6 , wherein each of the plurality of cavities comprises an aspect ratio of less than or equal to approximately 1 to 3.
11. A system comprising:
a processor; and
a memory device coupled to the processor and comprising:
a storage device; and
a transistor coupled to the storage device, wherein the transistor comprises:
a drain terminal comprising a doped polysilicon material disposed within a first shallow cavity formed in an isolation oxide region;
a source terminal comprising a polysilicon material disposed within a second shallow cavity formed in the isolation oxide region;
a channel formed in a silicon material and arranged between each of the first shallow cavity and the second shallow cavity, wherein the channel comprises a respective doped region coupled to each of the drain terminal and the source terminal; and
a gate disposed over the channel and comprising one or more conductive layers disposed over a gate oxide layer.
12. The system, as set forth in claim 11 , wherein each of the plurality of cavities comprises a depth in the range of approximately 300 angstroms to 1500 angstroms.
13. The system, as set forth in claim 11 , wherein each of the plurality of cavities comprises an aspect ratio of less than or equal to approximately 0.5 to 10.
14. The device, as set forth in claim 11 , wherein each of the plurality of cavities comprises an aspect ratio of less than or equal to approximately 1 to 3.