Latch-based random access memory (LBRAM) tri-state banking architecture
A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state output bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state output bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals. The memory produces an output signal dependent upon the enable signal generation logic output, and thus upon a logic level of the tri-state output bit line.
1. A memory, comprising:
a pair of bit lines addressable within a respective first and second banks of storage cells by a first portion of an address;
an enable signal generation logic adapted to produce a pair of enable signals upon receiving a second portion of the address; and
a pair of tri-state buffers coupled to receive respective said pair of bit lines and respective said pair of enable signals, and produce an output from the memory depending on a logic state of the pair of enable signals.
2. The memory as recited in claim 1 , wherein each of the storage cells comprise a latch.
3. The memory as recited in claim 1 , wherein the second portion of the address comprises at least one lesser significant bit or greater significant bit, and wherein the first portion of the address comprises all bits of the address greater than or less than, respectively, said at least one lesser significant bit or said at least one greater significant bit.
4. A random access memory, comprising:
a plurality of banks including a first bank and a second bank of latch storage cells, wherein the first bank has a first bit line and the second bank has a second bit line;
enable signal generation logic adapted to receive a portion of an address signal and configured to generate a first and second enable signals dependent upon the portion of the address signal;
a first tri-state buffer coupled to receive the first bit line and the first enable signal;
a second tri-state buffer coupled to receive the second bit line and the second enable signal; and
wherein the first and second tri-state buffers each comprise a tri-state output coupled to one another and configured to produce an output from the memory depending on the address signal and the first and second enable signals.
5. The random access memory as recited in claim 4 , wherein the output signal is indicative of a data value stored in the latch cells and accessed via the address signal.
6. The random access memory as recited in claim 4 , wherein the address signal comprises an ordered set of bits, and wherein the enable signal generation logic is adapted to receive one or more of the lowest ordered bits of the address signal and to generate the first and second enable signals dependent upon the one or more of the lowest ordered bits of the address signal.
7. The random access memory as recited in claim 4 , wherein the random access memory comprises a latch array divided to form the plurality of banks.
8. The random access memory as recited in claim 4 , wherein the first tri-state buffer drives the tri-state output to a logic level on the first bit line when the first enable signal is active, and wherein the second tri-state buffer drives the tri-state output to a logic level on the second bit line when the second enable signal is active.
9. The random access memory as recited in claim 4 , wherein the first tri-state buffer is coupled to receive a logical complement of the first enable signal, and wherein the second tri-state buffer is coupled to receive a logical complement of the second enable signal.
10. The random access memory as recited in claim 4 , wherein the random access memory comprises a 2 n ×m latch array divided to form p banks, wherein n≧1, m≧1, and p≧2.
11. The random access memory as recited in claim 10 , wherein each of the p banks comprises 2 n−k word lines where k=log 2 (p), and wherein the random access memory further comprises p decode units each coupled to the 2 n−k word lines of a corresponding one of the p banks.
12. The random access memory as recited in claim 11 , wherein the address signal comprises an ordered set of n bits, and wherein each of the p decode units is adapted to receive the highest-ordered (n−k) bits of the address signal and to activate one of the 2 n−k word lines of the corresponding one of the p banks dependent upon the highest-ordered (n−k) bits of the address signal.
13. The random access memory as recited in claim 10 , wherein the first bank has m bit lines, and the first bit line is one of the m bit lines of the first bank.
14. The random access memory as recited in claim 13 , wherein the second bank has m bit lines, and the second bit line is one of the m bit lines of the second bank.
15. The random access memory as recited in claim 14 , wherein the random access memory comprises a first set of m tri-state buffers, wherein the first tri-state buffer is one of the first set of m tri-state buffers.
16. The random access memory as recited in claim 15 , wherein the random access memory comprises a second set of m tri-state buffers, wherein the second tri-state buffer is one of the second set of m tri-state buffers.
17. The random access memory as recited in claim 16 , wherein the address signal comprises an ordered set of n bits, and wherein the enable signal generation logic is adapted to receive the lowest-ordered log 2 (p) bits of the address signal to generate p enable signals dependent upon the lowest-ordered log 2 (p) bits of the address signal, and wherein the first and second enable signals are part of the p enable signals.
18. A random access memory, comprising:
a 2 n ×m latch array divided to form p banks, wherein n≧1, m≧1, and p≧2, and wherein each of the p banks comprises (2 n−1 ·m) latch cells each configured to store data, 2 n−k word lines where k=log 2 (p), and m bit lines;
p decode units each coupled to the 2 n−k word lines of a corresponding one of the p banks, wherein each of the p decode units is adapted to receive (n−k) bits of an n-bit address signal and to activate one of the 2 n−k word lines of the corresponding one of the p banks dependent upon the (n−k) bits of the address signal;
enable signal generation logic adapted to receive k bits of the n-bit address signal and to generate p enable signals dependent upon the k bits of the address signal;
a first set of m tri-state buffers each having an input node coupled to a different one of the m bit lines of one of the p banks, an enable node coupled to receive a one of the p enable signals, and an output node coupled to a different one of m tri-state bit lines;
a second set of m tri-state buffers each having an input node coupled to a different one of the m bit lines of another one of the p banks, an enable node coupled to receive one of the p enable signals, and an output node coupled to a different one of the m tri-state bit lines; and
wherein the random access memory produces an output signal in response to the n-bit address signal and dependent upon a logic level of the tri-state bit line.
19. The random access memory as recited in claim 18 , wherein the output signal is indicative of a data value stored in the 2 n ×m latch array and accessed via the n-bit address signal.
20. The random access memory as recited in claim 18 , wherein each of the p decode units is adapted to receive the highest-ordered (n−k) bits of the n-bit address signal and to activate one of the 2 n−k word lines of the corresponding one of the p banks dependent upon the highest-ordered (n−k) bits of the address signal, and wherein the enable signal generation logic is adapted to receive the lowest-ordered k bits of the n-bit address signal and to generate p enable signals dependent upon the lowest-ordered k bits of the address signal.