IP Library Granted Patent US 7,270,867
Granted Patent B1
US 7,270,867 · App. 11/022,130 · Granted Sep 18, 2007

Leadless plastic chip carrier

Assignee: ASAT Ltd.
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Quick Facts
Patent No.
US 7,270,867
App. No.
11/022,130
Granted
Sep 18, 2007
Kind
B1
Abstract

A process for fabricating a leadless plastic chip carrier includes selectively depositing a plurality of base layers on a first surface of a base of a leadframe strip to at least partially define a die attach pad and at least one row of contact pads. At least one further layer is selectively deposited on portions of the plurality of layers to further define at least the contact pads. The leadframe strip is then treated with a surface preparation. A semiconductor die is mounted to the die attach pad, followed by wire bonding the semiconductor die to at least the contact pads. Molding the semiconductor die, the wire bonds, the die attach pad and the contact pads on the surface of the leadframe strip, in a molding compound follows. The leadframe strip is etched to expose the contact pads and the die attach pad and the leadless plastic chip carrier is singulated from a remainder of the leadframe strip.

Claims (50)

1. A prossess for fabricating a leadless plastic chip carrier, the process comprising:

selectively depositing a plurality of base layers on a first surface of a base of a leadframe strip to at least partially define a die attach pad and at least one row of contact pads; wherein selectively depositing said plurality of base layers comprises,

depositing a photo-imageable mask on said first surface of said leadframe strip;

imaging and developing said mask to define a plurality of pits in which said first surface is exposed; and

depositing successive layers of metal in said pits

selectively depositing at least one further layer on portions of said plurality of layers to further define at least said contact pads, wherein selectively depositing said at least one further layer comprises:

depositing a further photo-imageable mask on an outer surface of said base layers of metal;

imaging and developing said further photo-imageable mask to expose said contact pads;

depositing at least one further layer of metal on said contact pads; and

stripping said photo-imageable mask and said further photo-imageable mask;

treating said leadframe strip with a surface preparation;

mounting a semiconductor die to said die attach pad;

wire bonding said semiconductor die to at ones of the contact pads;

molding said semiconductor die, said wire bonds, said die attach pad and said contact pads on said surface of said leadframe strip, in a molding compound;

etching said base of said leadframe strip to expose said contact pads and said die attach pad;

singulating said leadless plastic chip carrier from a remainder of said leadframe strip.

2. The process according to claim 1 , wherein selectively depositing a plurality of base layers includes selectively depositing at least one layer of copper, and wherein said treating comprises dipping in a surface preparation to inhibit copper oxidation and promote bonding of copper to said molding compound.

3. The process according to claim 2 , wherein said treating comprises dipping in a surface preparation that reacts with copper to form an organo-metallic compound.

4. The process according to claim 1 , wherein selectively depositing a plurality of base layers includes selectively depositing at least one layer of copper, and wherein said treating comprises dipping in organic black oxide to inhibit copper oxidation.

5. The process according to claim 1 , wherein selectively depositing said at least one further layer comprises:

depositing a further photo-imageable mask on an outer surface of said base layers of metal;

imaging and developing said further photo-imageable mask to expose said contact pads and a peripheral portion of said die attach pad;

depositing at least one further layer of metal on said contact pads and on said peripheral portion of said die attach pad to define a ground ring; and

stripping said photo-imageable mask and said further photo-imageable mask.

6. The process according to claim 1 , wherein said wire bonding further comprises wire bonding said semiconductor die to said ground ring.

7. A process for fabricating a leadframe strip for use in fabricating an integrated circuit package, the process comprising:

selectively depositing a plurality of base layers on a first surface of a base of said leadframe strip to at least partially define a die attach pad and at least one row of contact pads, wherein said selectively depositing said plurality of base layers comprises:

depositing a photo-imageable mask on said first surface of said leadframe strip;

imaging and developing said mask to define a plurality of pits in which said first surface is exposed; and

depositing successive layers of metal in said pits;

selectively depositing at least one further layer on portions of said plurality of layers to further define at least said contact pads, wherein selectively depositing said at least one further layer comprises:

depositing a further photo-imageable mask on an outer surface of said base layers of metal;

imaging and developing said further photo-imageable mask to expose said contact pads;

depositing at least one further layer of metal on said contact pads; and

stripping said photo-imageable mask and said further photo-imageable mask; and

treating said leadframe strip with a surface preparation.

8. The process according to claim 7 , wherein selectively depositing a plurality of base layers includes selectively depositing at least one layer of copper, and wherein said treating comprises dipping in a surface preparation to inhibit copper oxidation and promote bonding of copper to said molding compound.

9. The process according to claim 8 , wherein said treating comprises dipping in a surface preparation that reacts with copper to form an organo-metallic compound.

10. The process according to claim 7 , wherein selectively depositing a plurality of base layers includes selectively depositing at least one layer of copper, and wherein said treating comprises dipping in organic black oxide to inhibit copper oxidation.

11. A process for fabricating a leadframe strip for use in fabricating an integrated circuit package, the process comprising:

selectively depositing a plurality of base layers on a first surface of a base of said leadframe strip to at least partially define a die attach pad and at least one row of contact pads, wherein said selectively depositing said plurality of base layers comprises:

depositing a photo-imageable mask on said first surface of said leadframe strip;

imaging and developing said mask to define a plurality of pits in which said first surface is exposed; and

depositing successive layers of metal in said pits;

selectively depositing at least one further layer on portions of said plurality of layers to further define at least said contact pads;

wherein selectively depositing said at least one further layer comprises:

depositing a further photo-imageable mask on an outer surface of said base layers of metal;

imaging and developing said further photo-imageable mask to expose said contact pads and a peripheral portion of said die attach pad;

depositing at least one further layer of metal on said contact pads and on said peripheral portion of said die attach pad to define a ground ring; and

stripping said photo-imageable mask and said further photo-imageable mask.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ADD ANNEX INADVERTENTLY LEFT OUT ORIGINAL ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED AT REEL: 037880 FRAME: 0534. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 8, 2016
From: UTAC HONG KONG LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 039822/0591 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2016
From: UTAC HONG KONG LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 037880/0534 →
CHANGE OF NAME Recorded Oct 29, 2010
From: ASAT LIMITED
To: UTAC HONG KONG LIMITED
Reel/Frame 025217/0406 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS - SECOND PRIORITY Recorded Jun 29, 2010
From: UTAC HONG KONG LIMITED
To: THE HONGKONG AND SHANGHAI BANKING CORPORATION LIMITED, AS SECURITY AGENT
Reel/Frame 024611/0097 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS - FIRST PRIORITY Recorded Jun 29, 2010
From: UTAC HONG KONG LIMITED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024599/0743 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS - SECOND PRIORITY Recorded Jun 29, 2010
From: UTAC HONG KONG LIMITED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024599/0827 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR FROM HO FAN, CHUN TO FAN, CHUN HO PREVIOUSLY RECORDED ON REEL 016703 FRAME 0826. ASSIGNOR(S) HEREBY CONFIRMS THE ERROR ON COVERSHEET DATA.. Recorded Nov 23, 2005
From: KWAN, KIN PUI; LAU, WING HIM; TSANG, KWOK CHEUNG; FAN, CHUN HO; MCLELLAN, NEIL
To: ASAT LTD.
Reel/Frame 016812/0354 →
DOCUMENT PREVIOUSLY RECORDED AT REEL 016014 FRAME 0441 CONTAINED ERRORS IN PATENT APPLICATION NUMBER 11/061895. DOCUMENT RERECORDED TO CORRECT ERRORS ON STATED REEL. Recorded Aug 9, 2005
From: KWAN, KIN PUI; LAU, WING HIM; TSANG, KWOK CHEUNG; HO FAN, CHUN; MCLELLAN, NEIL
To: ASAT LTD.
Reel/Frame 016703/0826 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2005
From: KWAN, KIN PUI; LAU, WING HIM; TSANG, KWOK CHEUNG; FAN, CHUN HO; MCLELLAN, NEIL
To: ASAT LTD.
Reel/Frame 016014/0441 →
Continuity (3)
Continuation In Part 0980267800 · Mar 9, 2001
Continuation In Part 0928835200 · Apr 8, 1999
Continuation In Part 0990580300 · Jun 10, 1998