IP Library › Granted Patent US 7,271,089
Granted Patent B2
US 7,271,089 · App. 10/932,156 · Granted Sep 18, 2007

Barrier layer, IC via, and IC line forming methods

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,271,089
App. No.
10/932,156
Granted
Sep 18, 2007
Kind
B2
Abstract

A barrier layer forming method includes providing a porous dielectric layer over a substrate, the dielectric layer having a surface with exposed pores, and treating the dielectric layer with a plasma formed from a methane-containing gas. The treating seals the exposed pores. The method includes depositing a barrier layer over the surface, the barrier layer being continuous over the sealed pores. The porous dielectric may be low K. The plasma may be formed at a bias of at least about 100 volts.

Claims (44)

1. A barrier layer forming method comprising:

providing a porous dielectric layer over a substrate and an opening in the dielectric layer, the opening having a sidewall and a bottom, the sidewall having exposed pores;

treating the dielectric layer with a plasma formed from a methane-containing gas, the treating sealing the exposed pores of the sidewall, but not sealing the bottom; and

depositing a barrier layer at least over the sidewall, the barrier layer being continuous over the sealed pores.

2. The method of claim 1 wherein the exposed pores comprise open pores.

3. The method of claim 1 further comprising providing a metal fill in the opening with metal containing copper and/or aluminum over the barrier layer, the barrier layer allowing less penetration of the metal into the dielectric layer compared to an otherwise identical barrier layer formed without the treating.

4. The method of claim 1 wherein the plasma is formed at a bias of at least about 100 volts.

5. The method of claim 1 wherein the treating deposits a carbon layer, sealing the exposed pores.

6. The method of claim 1 wherein the methane-containing gas does not comprise a halogen.

7. The method of claim 1 wherein the methane-containing gas consists of methane and, optionally, an inert carrier gas.

8. The method of claim 1 wherein depositing the barrier layer comprises atomic layer deposition.

9. The method of claim 1 wherein depositing the barrier layer comprises chemical vapor deposition.

10. The method of claim 1 wherein the barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof.

11. A barrier layer forming method comprising:

providing a porous, low K dielectric layer over a substrate and an opening in the dielectric layer, the opening having a sidewall and a bottom, the sidewall including open pores;

treating the dielectric layer with a plasma formed from a methane-containing gas at a bias of at least about 100 volts, the treating sealing the open pores of the sidewall, but not sealing the bottom; and

depositing a barrier layer at least over the sidewall, the barrier layer being continuous over the sealed pores.

12. The method of claim 11 wherein the substrate includes an electrical node and the opening is formed through the dielectric layer to expose the node.

13. The method of claim 11 wherein providing the opening comprises a dual damascene process and provides a trench and a via opening.

14. The method of claim 11 wherein the treating deposits a carbon layer, sealing the open pores.

15. The method of claim 11 wherein the methane-containing gas does not comprise a halogen.

16. The method of claim 11 wherein the methane-containing gas consists of methane and, optionally, an inert carrier gas.

17. The method of claim 11 further comprising providing a metal fill in the opening with metal containing copper and/or aluminum over the barrier layer, the barrier layer allowing less penetration of the metal into the dielectric layer compared to an otherwise identical barrier layer formed without the treating.

18. The method of claim 17 wherein the metal fill forms a conductive via.

19. The method of claim 17 wherein the metal fill forms a conductive line extending across the dielectric layer and connecting electrical nodes.

20. The method of claim 11 wherein depositing the barrier layer comprises atomic layer deposition.

21. The method of claim 11 wherein depositing the barrier layer comprises chemical vapor deposition.

22. The method of claim 11 wherein the barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof.

23. An integrated circuit via forming method comprising:

providing a porous, low K dielectric layer over a semiconductive substrate including an electrical node;

forming a masking layer over the dielectric layer and patterning the masking layer to expose a portion of the dielectric layer;

forming a via opening through the exposed portion of the dielectric layer to expose the node, the opening having a sidewall including open pores;

removing the patterned masking layer;

treating the dielectric layer with a plasma formed from a methane-containing gas at a bias of at least about 100 volts, the treating depositing a carbon layer sealing the open pores of the sidewall but not depositing a carbon layer over the node;

atomic layer depositing a barrier layer at least over the sidewall, the barrier layer being continuous over the sealed pores; and

filling the opening with metal containing copper and/or aluminum over the barrier layer and in electrical connection with the node, the metal fill forming a conductive via to the node.

24. The method of claim 23 wherein the patterned masking layer is removed before the treating.

25. The method of claim 23 wherein the patterned masking layer is removed after the treating.

26. The method of claim 23 wherein forming the via opening comprises a dual damascene process and further provides a trench.

27. The method of claim 26 wherein the metal fill further forms a conductive line in the trench extending across the dielectric layer and connecting electrical nodes.

28. The method of claim 23 wherein the methane-containing gas does not comprise a halogen.

29. The method of claim 23 wherein the methane-containing gas consists of methane and, optionally, an inert carrier gas.

30. The method of claim 23 wherein the barrier layer allows less penetration of the metal into the dielectric layer compared to an otherwise identical barrier layer formed without the treating.

31. The method of claim 23 wherein the barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2004
From: SANDHU, GURTEJ S.; HOWARD, BRADLEY J.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 015762/0748 →
Continuity (1)
Related Publication 20060046472A1 · Mar 2, 2006