Decoding techniques for read-only memory
A memory circuit includes a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of column sense logic units are also provided, corresponding to the bit line structures. Each of the column sense logic units includes a first logic gate and a second logic gate. The first logic gate has a first input connected with a first one of the bit lines and a second input connected with a second one of the bit lines. The second logic gate has a first input interconnected with a third one of the bit lines, and a second input interconnected with the second one of the bit lines.
1. A memory circuit, comprising:
a plurality of bit line structures, each of said bit line structures comprising at least three bit lines;
a plurality of word lines, said word lines intersecting with said bit line structures at a plurality of sites;
a plurality of switching devices, individual ones of said switching devices being located at selected ones of said sites and being connected between an adjacent one of said word lines and a selected one of said bit lines of an adjacent one of said bit line structures for selective electrical conduction therebetween upon activation by said adjacent one of said word lines; and
a plurality of column sense logic units, each of said column sense logic units being associated with a corresponding one of said bit line structures, each of said column sense logic units in turn comprising:
a first logic gate having a first input electrically interconnected with a first one of said bit lines in said corresponding one of said bit line structures and a second input electrically interconnected with a second one of said bit lines in said corresponding one of said bit line structures; and
a second logic gate having a first input electrically interconnected with a third one of said bit lines in said corresponding one of said bit line structures and a second input electrically interconnected with said second one of said bit lines in said corresponding one of said bit line structures.
2. The memory circuit of claim 1 , wherein said circuit is formed as an integrated circuit.
3. The memory circuit of claim 1 , wherein:
with respect to a given one of said column sense logic units, said first one of said bit lines is designated as A, said second one of said bit lines is designated as C, and said third one of said bit lines is designated as B; and
each of said sites is configured to store at least two bits of information, said information being encoded according to the following table:
bit line A
bit line B
bit line C
bit 0
bit 1
inactive
inactive
inactive
0
0
active
inactive
inactive
0
1
inactive
active
inactive
1
0
inactive
inactive
active
1
1.
4. The memory circuit of claim 3 , wherein said first logic gate is configured to decode said bit 1 and said second logic gate is configured to decode said bit 0 .
5. The memory circuit of claim 3 , wherein each of said first logic gates and each of said second logic gates has an output, further comprising a column multiplexer electrically interconnected with said outputs of said first and second logic gates, said column multiplexer being configured to select which of said column sense logic units to read from.
6. The memory circuit of claim 5 , wherein said outputs of said logic gates are available to said multiplexer substantially immediately following said activation of said adjacent one of said word lines.
7. The memory circuit of claim 3 , wherein said switching devices comprise field effect transistors (FETs).
8. The memory circuit of claim 7 , wherein said FETs comprise n-type FETs (NFETS).
9. The memory circuit of claim 8 , wherein said “inactive” entry in said table denotes a logical “high” state and said “active” entry in said table denotes a logical “low” state.
10. The memory circuit of claim 9 , wherein said “low” state is achieved via pull-down through a corresponding one of said NFETs.
11. The memory circuit of claim 3 , wherein said first and second logic gates comprise NAND gates.
12. The memory circuit of claim 1 , wherein said individual ones of said switching devices are connected between said adjacent one of said word lines and said selected one of said bit lines of said adjacent one of said bit line structures via a programmable contact window.
13. The memory circuit of claim 1 , wherein said circuit is formed as an integrated circuit.
14. A semiconductor wafer comprising a plurality of integrated circuits, at least one of the plurality of integrated circuits comprising:
a plurality of bit line structures, each of said bit line structures comprising at least three bit lines;
a plurality of word lines, said word lines intersecting with said bit line structures at a plurality of sites;
a plurality of switching devices, individual ones of said switching devices being located at selected ones of said sites and being connected between an adjacent one of said word lines and a selected one of said bit lines of an adjacent one of said bit line structures for selective electrical conduction therebetween upon activation by said adjacent one of said word lines;
a plurality of column sense logic units, each of said column sense logic units being associated with a corresponding one of said bit line structures, each of said column sense logic units in turn comprising:
a first logic gate having a first input electrically interconnected with a first one of said bit lines in said corresponding one of said bit line structures and a second input electrically interconnected with a second one of said bit lines in said corresponding one of said bit line structures; and
a second logic gate having a first input electrically interconnected with a third one of said bit lines in said corresponding one of said bit line structures and a second input electrically interconnected with said second one of said bit lines in said corresponding one of said bit line structures.
15. A computing apparatus, comprising:
a memory;
an input output device; and
at least one processor, coupled to said memory and said input output device and operative to execute instructions, at least some of said instructions being stored in said memory;
wherein said memory in turn comprises:
a plurality of bit line structures, each of said bit line structures comprising at least three bit lines;
a plurality of word lines, said word lines intersecting with said bit line structures at a plurality of sites;
a plurality of switching devices, individual ones of said switching devices being located at selected ones of said sites and being connected between an adjacent one of said word lines and a selected one of said bit lines of an adjacent one of said bit line structures for selective electrical conduction therebetween upon activation by said adjacent one of said word lines; and
a plurality of column sense logic units, each of said column sense logic units being associated with a corresponding one of said bit line structures, each of said column sense logic units in turn comprising:
a first logic gate having a first input electrically interconnected with a first one of said bit lines in said corresponding one of said bit line structures and a second input electrically interconnected with a second one of said bit lines in said corresponding one of said bit line structures; and
a second logic gate having a first input electrically interconnected with a third one of said bit lines in said corresponding one of said bit line structures and a second input electrically interconnected with said second one of said bit lines in said corresponding one of said bit line structures.
16. A method of operating a memory circuit, comprising the steps of:
providing a memory circuit comprising:
a plurality of bit line structures, each of said bit line structures comprising at least three bit lines;
a plurality of word lines, said word lines intersecting with said bit line structures at a plurality of sites;
a plurality of switching devices, individual ones of said switching devices being located at selected ones of said sites and being connected between an adjacent one of said word lines and a selected one of said bit lines of an adjacent one of said bit line structures for selective electrical conduction therebetween upon activation by said adjacent one of said word lines;
a plurality of column sense logic units, each of said column sense logic units being associated with a corresponding one of said bit line structures, each of said column sense logic units in turn comprising:
a first logic gate having an output and having a first input electrically interconnected with a first one of said bit lines in said corresponding one of said bit line structures and a second input electrically interconnected with a second one of said bit lines in said corresponding one of said bit line structures; and
a second logic gate having an output and having a first input electrically interconnected with a third one of said bit lines in said corresponding one of said bit line structures and a second input electrically interconnected with said second one of said bit lines in said corresponding one of said bit line structures; and
a column multiplexer electrically interconnected with said outputs of said first and second logic gates, said column multiplexer being configured to select which of said column sense logic units to read from;
activating a given one of said word lines; and
making said outputs of said logic gates available to said multiplexer substantially immediately following activation of said given one of said word lines.
17. The method of claim 16 , further comprising the additional step of selecting which of said column sense logic units to read from, with said multiplexer.
18. The method of claim 17 , wherein, with respect to a given one of said column sense logic units, said first one of said bit lines is designated as A, said second one of said bit lines is designated as C, and said third one of said bit lines is designated as B, and each of said sites is configured to store at least two bits of information;
further comprising the additional step of decoding said outputs of said logic gates according to the following table:
bit line A
bit line B
bit line C
bit 0
bit 1
inactive
inactive
inactive
0
0
active
inactive
inactive
0
1
inactive
active
inactive
1
0
inactive
inactive
active
1
1.