Granted Patent B2

US 7,348,621 · App. 11/351,520 · Granted Mar 25, 2008

Abstract

Claims (23)

1. A non-volatile memory cell comprising:

a substrate of a first conductivity type;

a first dopant region of a second conductivity type in the substrate;

a second dopant region of the first conductivity type in the first dopant region;

a first isolation region overlaying a first portion of the substrate, the first dopant region, and the second dopant region, the first isolation region being in contact with the substrate, the first dopant region, and the second dopant region;

a second isolation region overlaying a second portion of the substrate, the first dopant region, and the second dopant region, the first isolation region being in contact with the substrate, the first dopant region, and the second dopant region;

a contact region of the first conductivity type in the second dopant region, the contact region extending between the first isolation region and the second isolation region such that the first isolation region and the second isolation region are both in contact with the contact region, the contact region being more heavily doped than the second dopant region;

a first gate dielectric atop the first isolation region and a portion of the contact region; and

a first gate conductor atop the first gate dielectric.

2. The non-volatile memory cell of claim 1 , further comprising:

a third dopant region of the first conductivity type in the substrate;

a second gate dielectric atop the third dopant region;

a second gate conductor atop the second gate dielectric, the second gate conductor being coupled to the first gate conductor;

a source region of the second conductivity type in the third dopant region, the source region being being contact with the second gate dielectric; and

a drain region of the second conductivity type in the third dopant region, the drain region being in contact with the second gate dielectric.

3. The non-volatile memory cell of claim 2 , wherein the first gate conductor and the second gate conductor comprise part of a single conducting trace.

4. The non-volatile memory cell of claim 2 , wherein the source region and the drain region are symmetrical.

5. The non-volatile memory cell of claim 2 , wherein the source region and the drain region comprise only arsenic.

6. The non-volatile memory cell of claim 2 , further comprising:

a plurality of spacers, wherein a first of the plurality of spacers is only in contact with the second gate dielectric, the second gate conductor, and the source region and a second of the plurality of spacers is only in contact with the second gate dielectric, the second gate conductor, and the drain region.

7. The non-volatile memory cell of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.

8. The non-volatile memory cell of claim 1 , wherein the second dopant region, the contact region, the first gate dielectric, and the first gate conductor form a coupling capacitor.

9. The non-volatile memory cell of claim 1 , wherein the non-volatile memory cell does not include any lightly-doped drain regions.

Assignments (10)