Data communication method and data communication device and semiconductor device
The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method includes: a step of encoding data of N bits (N being 2 or larger) to transmission data of M bits (M being 3 or larger) on a transmission side; a step of generating a transmission signal in which transition takes place in at least one level of any of the transmission data synchronously with a transmission clock and transmitting the transmission signal to a transmission line on the transmission side; a step of recognizing transition in the signal of M bits received via the transmission line and detecting the reception data of M bits synchronized with the transmission clock on a reception side; and a step of decoding the reception data of M bits to the data of N bits.
1. A data communication device comprising:
a transmission-side device including an encoder which encodes data of N parallel bits (N being 2 or larger) to transmission data of M parallel bits (M being 3 or larger), and a transmission circuit which outputs a transmission signal in which transition takes place in at least one level of any of said transmission data synchronously with a transmission clock;
a transmission line to which the transmission signal of said transmission circuit is transmitted; and
a reception-side device including a reception circuit which recognizes transition in a reception signal of said M bits received via said transmission line and which detects the reception data of said M bits corresponding to said transmission clock and a decoder which decodes said reception data to said N-bit data,
wherein M is larger than N,
wherein said encoder generates transmission data in which at least one bit out of M bits has a first binary logic value,
wherein said transmission circuit generates said transmission signal which shifts the level of the data having said first binary logic value out of said M-bit transmission data synchronously with said transmission clock and which maintains the data having a second binary logic value at the same level,
wherein said encoder generates transmission data in which the number of bits having said first logic value is two or more, and
wherein said reception circuit comprises:
a plurality of first MOSFETs connected in parallel which receive said reception signal of M bits, and each said first MOSFET having a conductance characteristic substantially equal to a first value; and
a plurality of second MOSFETs connected in parallel, the number of second MOSFETs being M, and M−1 of said second MOSFETs each having a conductance characteristic substantially equal to said first value, and a remaining second MOSFET has a conductance characteristic which is substantially equal to one half the first value,
wherein a voltage corresponding to one of two levels of said reception signal is supplied to gates of said first MOSFETs which correspond to the number of bits having said first binary logic value, including the remaining second MOSFET,
wherein a voltage corresponding to the other level of the reception signal is supplied to the gates of the remaining MOSFETs, and
wherein the reception circuit further includes a circuit which detects a difference between a first current flowing in said first MOSFETs and a second current flowing in said second MOSFETs and generates a detection signal indicative of validity/invalidity of the reception signal.