Method and apparatus for sensing flash memory using delta sigma modulation
A simple method and device for accurately measuring flash memory cell current. The sensing scheme comprises an integrator, an analog to digital converter, and a digital to analog converter. The method comprises the acts of applying an input current and a feedback output current to a summer, integrating the resulting summer output over time, passing the integrated output to a clocked comparator, outputting a comparator output which controls a feedback circuit that keeps the integrator's voltage at the same level as a reference voltage, and outputting a digital average current to a counter. Delta sigma modulation (averaging) is employed to cancel out noise that would otherwise affect the cell current measurement.
1. A sense amplifier circuit comprising:
a first circuit for summing a current from a memory cell and a feedback current to form a summed current;
an integrator connected to receive the summed current and to integrate the summed current over a first time, said integrator being charged and discharged during the first time;
an analog-to-digital converter connected to receive the integrated summed current and having a digital output corresponding to an average current and a count of a number of times said integrator is discharged during the first time; and
a digital-to-analog converter connected to receive the digital average current and to output the feedback current to the first circuit.
2. The sense amplifier circuit of claim 1 , wherein said integrator comprises a capacitor.
3. The sense amplifier circuit of claim 1 , wherein said integrator is bitline capacitance.
4. The sense amplifier circuit of claim 1 , wherein said analog-to-digital converter comprises a clocked comparator.
5. The sense amplifier circuit of claim 1 , wherein said digital-to-analog converter comprises a current source and a switch, said switch being controlled to switch in said current source in response to the digital average current.
6. The sense amplifier circuit of claim 1 , wherein the memory cell comprises a flash memory cell.
7. The sense amplifier circuit of claim 1 , wherein the memory cell comprises a floating gate device.
8. The sense amplifier circuit of claim 1 , further comprising a counter for using the digital output.
9. A method of sensing a state of a memory cell, said method comprising the steps of:
combining a memory cell current with a feedback average current to form a first output,
integrating the first output to form a second output using an integrator, the integrator being charged and discharged during the integrating,
converting the second output to a digital average current output, and
using the digital average output to form and output the feedback average current,
wherein the digital average output corresponds to a count of a number of times an integrator used to integrate the first output is discharged.
10. The method of claim 9 , wherein said digital average current is fed to a counter.
11. The method of claim 9 , wherein said digital average current is equivalent to said first output.
12. The method of claim 9 , wherein said combining act is performed by summing the memory cell current with the feedback current.
13. The method of claim 9 , wherein said act of converting the second output to a digital average current output is performed by comparing the output to a reference voltage.
14. The method of claim 9 , wherein said memory cell current is flash cell current and said feedback average current is an average cell current.
15. A processor system comprising:
a processor; and
a memory device coupled to the processor, said memory device comprising a sense amplifier circuit comprising:
a first circuit for summing a current from a memory cell and a feedback current to form a summed current;
an integrator connected to receive the summed current and to integrate the summed current over a first time, said integrator being charged and discharged during the first time;
an analog-to-digital converter connected to receive the integrated summed current and having a digital output corresponding to an average current and a count of a number of times said integrator is discharged during the first time; and
a digital-to-analog converter connected to receive the digital average current and to output the feedback current to the first circuit.
16. The processor system of claim 15 , wherein said integrator is a capacitor.
17. The processor system of claim 15 , wherein said integrator is bitline capacitance.
18. The processor system of claim 15 , wherein said analog-to-digital converter comprises a clocked comparator.
19. The processor system of claim 15 , wherein said digital-to-analog converter comprises a current source and a switch, said switch being controlled to switch in said current source in response to the digital average current.
20. The processor system of claim 15 , wherein the memory cell comprises a flash memory cell.
21. The processor system of claim 15 , wherein the memory cell comprises a floating gate device.
22. The processor system of claim 15 , further comprising a counter for using the digital output.
23. A memory device comprising:
a flash memory cell; and
a sense amplifier circuit connected to the cell, the sense amplifier circuit comprising:
a first circuit for summing a current from a memory cell and a feedback current to form a summed current;
an integrator connected to receive the summed current and to integrate the summed current over a first time, said integrator being charged and discharged during the first time;
an analog-to-digital converter connected to receive the integrated summed current and having a digital output corresponding to an average current and a count of a number of times said integrator is discharged during the first time; and
a digital-to-analog converter connected to receive the digital average current and to output the feedback current to the first circuit.
24. The memory device of claim 23 , wherein said integrator comprises a capacitor.
25. The memory device of claim 23 , wherein said integrator is bitline capacitance.
26. The memory device of claim 23 , wherein said analog-to-digital converter comprises a clocked comparator.
27. The memory device of claim 23 , wherein said digital-to-analog converter comprises a current source and a switch, said switch being controlled to switch in said current source in response to the digital average current.
28. The memory device of claim 23 , wherein the memory cell comprises a flash memory cell.
29. The memory device of claim 23 , wherein the memory cell comprises a floating gate device.
30. The memory device of claim 23 , further comprising a counter for using the digital output.
31. A memory device comprising:
an array of flash memory cells; and
a sense amplifier circuit connected to a column of said flash memory cells, the sense amplifier circuit comprising:
a first circuit for summing a current from a memory cell and a feedback current to form a summed current;
an integrator connected to receive the summed current and to integrate the summed current over a first time, said integrator being charged and discharged during the first time;
an analog-to-digital converter connected to receive the integrated summed current and having a digital output corresponding to an average current and a count of a number of times said integrator is discharged during the first time; and
a digital-to-analog converter connected to receive the digital average current and to output the feedback current to the first circuit.
32. The memory device of claim 31 , wherein said integrator comprises a capacitor.
33. The memory device of claim 31 , wherein said integrator is bitline capacitance.
34. The memory device of claim 31 , wherein said analog-to-digital converter comprises a clocked comparator.
35. The memory device of claim 31 , wherein said digital-to-analog converter comprises a current source and a switch, said switch being controlled to switch in said current source in response to the digital average current.
36. The memory device of claim 31 , wherein the array of memory cells comprises an array of flash memory cells.
37. The memory device of claim 31 , wherein the array of memory cells comprises floating gate devices.
38. The memory device of claim 31 , further comprising a counter for using the digital output.
39. The memory device of claim 31 , further comprising a plurality of sense amplifier circuits connected to each of said flash memory cells.