Selective epitaxy vertical integrated circuit components
Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of the component body. These components are grown directly in electrical communication lines. Moreover, these components are adapted for use in memory devices and are believed to not require the use of shallow trench isolation.
1. A vertical memory cell, comprising:
a substantially planar surface;
a first insulator adjacent the planar surface,
a second insulator spaced apart from the first insulator, wherein an annular depression is formed in the first insulator and the second insulator;
an access device including a mesa, the mesa formed partly within the annular depression and extending outwardly from the planar surface;
a buried conductive path bounded by the first insulator and the second insulator, the buried conductive path enclosing a section of the mesa, the mesa circumferentially contacting the buried conductive path at a specified radius along a vertical sidewall region of the mesa above the first insulator, wherein a portion of the mesa extending radially inward from the buried conductive path and extending vertically along the buried conductive path between the first insulator and the second insulator consists essentially of dopant atoms of one conductivity type, and wherein the dopant atoms in the portion form with a diffused concentration profile in the radial direction; and
a storage device on the mesa.
2. The memory cell of claim 1 , wherein the first and the second insulators are configured to permit current in the buried conductive path to flow into the mesa only across the specified radius.
3. The memory cell of claim 1 , wherein the annular depression is formed with a uniform radius.
4. The memory cell of claim 1 , wherein the annular depression is formed having the specified radius.
5. The memory cell of claim 1 , wherein the buried conductive path contacts the mesa along the circumference only between the first and the second insulators.
6. The memory cell of claim 1 , wherein the buried conductive path is a bit line conductor.
7. The memory cell of claim 1 , wherein the mesa electrically contacts the buried conductive path only along the vertical sidewall region above the first insulator.
8. The memory cell of claim 1 , wherein the mesa includes a diffused dopant concentration profile in a vertical region configured to contact the storage device.
9. A vertical memory cell, comprising:
a substantially planar surface;
a first insulator adjacent the planar surface;
a second insulator spaced apart from the first insulator, wherein the first insulator and the second insulator are used to form a portion of the annular recess;
an access device including a mesa, the mesa formed partly within the annular recess and extending outwardly from the planar surface;
a buried conductive path confined by the first insulator and the second insulator, the buried conductive path enclosing a section of the mesa, the mesa circumferentially contacting the buried conductive path at a specified radius along a vertical sidewall region of the mesa above the first insulator, wherein a portion of the mesa extending radially inward from the buried conductive path and extending vertically along the buried conductive path between the first insulator and the second insulator consists essentially of dopant atoms of one conductivity type, and wherein the dopant atoms in the portion arrange in an abrupt concentration profile in the radial direction; and
a storage device on the mesa.
10. The memory cell of claim 9 , wherein the first and the second insulators are configured to permit a voltage transmitted along in the buried conductive path to couple to the mesa only at the specified radius.
11. The memory cell of claim 9 , wherein the annular recess is formed with a specified radius.
12. The memory cell of claim 9 , wherein the annular recess is formed having the specified radius.
13. The memory cell of claim 9 , wherein the buried conductive path contacts the mesa only along the circumference between the first and the second insulators.
14. The memory cell of claim 9 , wherein the buried conductive path is a bit line conductor.
15. The memory cell of claim 9 , wherein the mesa is configured to electrically contact the buried conductive path only along the vertical sidewall region above the first insulator.