IP Library › Granted Patent US 7,374,993
Granted Patent B2
US 7,374,993 · App. 10/695,959 · Granted May 20, 2008

Methods of forming capacitors

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,374,993
App. No.
10/695,959
Granted
May 20, 2008
Kind
B2
Abstract

A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the first capacitor electrode. The capacitor dielectric region has an exposed oxide containing surface. The exposed oxide containing surface of the capacitor dielectric region is treated with at least one of a borane or a silane. A second capacitor electrode is deposited over the treated oxide containing surface. The second capacitor electrode has an inner metal surface contacting against the treated oxide containing surface. Other aspects and implementations are contemplated.

Claims (54)

1. A method of forming a capacitor, comprising:

forming a first capacitor electrode over a semiconductor substrate;

forming a capacitor dielectric region onto the first capacitor electrode, the capacitor dielectric region comprising an exposed oxide-containing surface;

treating the exposed oxide-containing surface of the capacitor dielectric region with at least one of a borane or a silane without depositing any layer onto the exposed oxide-containing surface during any of said treating; and

after said treating with at least one of the borane or the silane without depositing any layer onto the exposed oxide-containing surface during any of said treating, then forming a second capacitor electrode over the treated oxide-containing surface, the second capacitor electrode comprising an inner metal surface contacting against the treated oxide-containing surface, the depositing the second capacitor electrode comprises using a halogen-containing gas, said treating of the exposed oxide-containing surface of the capacitor dielectric region being effective to reduce halogen incorporation into the capacitor dielectric region than would otherwise occur in the absence of said treating.

2. The method of claim 1 wherein the first capacitor electrode consists essentially of semiconductive material.

3. The method of claim 1 wherein the first capacitor electrode consists essentially of metal.

4. The method of claim 1 wherein the exposed oxide-containing surface comprises hafnium oxide.

5. The method of claim 1 wherein the exposed oxide-containing surface comprises aluminum oxide.

6. The method of claim 1 wherein the treating is with at least one borane.

7. The method of claim 6 wherein all borane used during the treating is void of halogen.

8. The method of claim 6 wherein the borane is selected from the group consisting of BH 3 , B 2 H 6 , B 4 H 10 , B 5 H 9 , B 6 H 10 and B 10 H 14 , and mixtures thereof.

9. The method of claim 1 wherein the treating is with at least one silane.

10. The method of claim 9 wherein all silane used during the treating is void of halogen.

11. The method of claim 9 wherein the silane is selected from the group consisting of SiH 4 , Si 2 H 6 , Si 3 H 8 and Si 4 H 10 , and mixtures thereof.

12. The method of claim 1 wherein the treating comprises a temperature from 200° C. to 500° C., and a pressure from 1 Torr to 100 Torr.

13. The method of claim 1 wherein the treating is for at least 1 second.

14. The method of claim 1 wherein the treating is for at least 10 seconds.

15. The method of claim 1 wherein the inner metal surface comprises an elemental metal or an alloy of elemental metals.

16. The method of claim 15 wherein the inner metal surface comprises tungsten.

17. The method of claim 1 wherein the inner metal surface comprises a conductive metal compound.

18. The method of claim 17 wherein the inner metal surface comprises TiN.

19. The method of claim 1 wherein the second capacitor electrode consists essentially of metal.

20. The method of claim 1 comprising conducting the treating to be effective to reduce leakage current of the capacitor than would otherwise occur in the absence of said treating.

21. The method of claim 1 wherein the exposed oxide-containing surface comprises OH groups, the treating being effective to passivate said OH groups.

22. The method of claim 1 wherein the first capacitor electrode consists essentially of semiconductive material and the second capacitor electrode consists essentially of metal thereby forming an MIS capacitor.

23. The method of claim 1 wherein the first capacitor electrode consists essentially of metal and the second capacitor electrode consists essentially of metal thereby forming an MIM capacitor.

24. The method of claim 1 wherein the treating is with at least one borane and with at least one silane.

25. A method of forming a capacitor, comprising:

forming a first capacitor electrode over a semiconductor substrate;

forming a capacitor dielectric region onto the first capacitor electrode, the capacitor dielectric region comprising an exposed oxide-containing surface;

treating the exposed oxide-containing surface of the capacitor dielectric region with at least one of a borane or a silane at a temperature from 200° C. to 500° C. and a pressure from 1 Torr to 100 Torr for at least 1 second, the treating being void of depositing any layer onto the exposed oxide-containing surface during any of said treating; and

after said treating with at least one of the borane or the silane which is void of depositing any layer onto the exposed oxide-containing surface during any of said treating, then forming a second capacitor electrode consisting essentially of metal over the treated oxide-containing surface, the second capacitor electrode comprising an inner metal surface contacting against the treated oxide-containing surface, the depositing the second capacitor electrode comprises using a halogen-containing gas, said treating of the exposed oxide-containing surface of the capacitor dielectric region being effective to reduce halogen incorporation into the capacitor dielectric region than would otherwise occur in the absence of said treating.

26. The method of claim 25 wherein the exposed oxide-containing surface comprises hafnium oxide.

27. The method of claim 25 wherein the exposed oxide-containing surface comprises aluminum oxide.

28. The method of claim 25 wherein the treating is with at least one borane.

29. The method of claim 28 wherein all borane used during the treating is void of halogen.

30. The method of claim 28 wherein the borane is selected from the group consisting of BH 3 , B 2 H 6 , B 4 H 10 , B 5 H 9 , B 6 H 10 and B 10 H 14 , and mixtures thereof.

31. The method of claim 25 wherein the treating is with at least one silane.

32. The method of claim 31 wherein all silane used during the treating is void of halogen.

33. The method of claim 31 wherein the silane is selected from the group consisting of SiH 4 , Si 2 H 6 , Si 3 H 8 and Si 4 H 10 , and mixtures thereof.

34. The method of claim 25 wherein the treating is for at least 10 seconds.

35. The method of claim 25 wherein the inner metal surface comprises an elemental metal or an alloy of elemental metals.

36. The method of claim 35 wherein the inner metal surface comprises tungsten.

37. The method of claim 25 wherein the inner metal surface comprises a conductive metal compound.

38. The method of claim 37 wherein the inner metal surface comprises TiN.

39. The method of claim 25 wherein the treating is effective to reduce leakage current of the capacitor than would otherwise occur in the absence of said treating.

40. The method of claim 25 wherein the exposed oxide-containing surface comprises OH groups, the treating being effective to passivate said OH groups.

41. The method of claim 25 wherein the treating is with at least one borane and with at least one silane.

42. A method of forming a capacitor, comprising:

forming a first capacitor electrode over a semiconductor substrate;

forming a capacitor dielectric region onto the first capacitor electrode, the capacitor dielectric region comprising an exposed oxide-containing surface;

treating the exposed oxide-containing surface of the capacitor dielectric region with at least one borane and with at least one silane; and

forming a second capacitor electrode over the treated oxide-containing surface, the second capacitor electrode comprising an inner metal surface contacting against the treated oxide-containing surface, the depositing the second capacitor electrode comprises using a halogen-containing gas, said treating of the exposed oxide-containing surface of the capacitor dielectric region being effective to reduce halogen incorporation into the capacitor dielectric region than would otherwise occur in the absence of said treating.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2003
From: MILLER, MATTHEW W.; BASCERI, CEM
To: MICRON TECHNOLOGY, INC.
Reel/Frame 014658/0572 →
Continuity (1)
Related Publication 20050090069A1 · Apr 28, 2005