IP Library Granted Patent US 7,384,566
Granted Patent B2
US 7,384,566 · App. 11/121,091 · Granted Jun 10, 2008

Fabrication method for printed circuit board

Assignee: Advanced Semiconductor Engineering Inc.
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Quick Facts
Patent No.
US 7,384,566
App. No.
11/121,091
Granted
Jun 10, 2008
Kind
B2
Abstract

A fabrication method for PCBs. The method includes providing a substrate having a layout area and a periphery area around the layout area on a surface, forming a patterned wiring layer, having a bus line in the periphery area, a plurality of pads in the layout area, a plurality of bridge lines providing electrical connection between the pads, and a plating line electrically connecting the bus line and pads, overlying the substrate, forming a patterned solder mask over the substrate and wiring layer, the patterned solder mask having a plurality of first openings respectively exposing the pads and plating a metal layer respectively overlying the pads, forming a plurality of second openings respectively exposing the bridge lines between the pads, and removing the exposed bridge lines.

Claims (16)

1. A fabrication method for printed circuit boards (PCBs), comprising:

providing a substrate having a layout area and a periphery area around the layout area on a surface;

forming a patterned wiring layer, having a bus line in the periphery area, a plurality of pads in the layout area, a plurality of straight bridge lines providing electrical connection between the pads, a branch bridge line providing electrical connection between a node in one of the straight bridge lines and one of the pads, and a plating line electrically connecting the bus line and pads, overlying the substrate, wherein the bus line surrounds the layout area, each of the straight bridge line is disposed in the layout area and has two ends for being physically connected to the two adjacent pads;

forming a patterned solder mask over the substrate and wiring layer, the patterned solder mask having a plurality of first openings respectively exposing the pads;

plating a metal layer respectively overlying the pads;

forming a plurality of second openings in the solder mask, respectively exposing the straight bridge lines between the pads, the plating line between the bus line and pads, and the node; and

removing the exposed straight bridge lines, plating line, and node.

2. The method as claimed in claim 1 , wherein the plating line is disposed between the bus line and at least one of the pads.

3. The method as claimed in claim 1 , wherein the plating line is disposed between the bus line and at least one of the straight bridge lines.

4. The method as claimed in claim 1 , wherein the plating line is between the bus line and the branch straight bridge lines.

5. The method as claimed in claim 1 , wherein the first openings are formed by photolithography.

6. The method us claimed in claim 1 , wherein the metal layer comprises Ni/Au.

7. The method as claimed in claim 1 , wherein the second openings are formed by laser absorbing.

8. The method as claimed in claim 1 , wherein the second openings are formed by photolithography.

9. The method as claimed in claim 1 , wherein the exposed straight bridge lines, plating line, and node are removed by etching.

10. The method as claimed in claim 1 , wherein the exposed straight bridge lines, plating line, and node are removed by laser absorbing.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2008
From: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
To: ASE (SHANGHAI) INC.
Reel/Frame 021518/0063 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2005
From: CHEN, HUNG-NAN; FANG, JEN-KUANG; LO, KUANG-LIN
To: ADVANCED SEMICONDUCTOR ENGINEERING INC.
Reel/Frame 016531/0285 →
Priority Claims (1)
TW 93112869 A · May 7, 2004 · national
Continuity (1)
Related Publication 20050246892A1 · Nov 10, 2005