IP Library Granted Patent US 7,390,756
Granted Patent B2
US 7,390,756 · App. 11/117,121 · Granted Jun 24, 2008

Atomic layer deposited zirconium silicon oxide films

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,390,756
App. No.
11/117,121
Granted
Jun 24, 2008
Kind
B2
Abstract

A dielectric layer containing an atomic layer deposited zirconium silicon oxide film disposed in an integrated circuit and a method of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. Embodiments include forming zirconium silicates as dielectric layers in devices in an integrated circuit. In an embodiment, a zirconium silicon oxide film is formed by atomic layer deposition using a zirconium precursor containing silicon and a silicon precursor. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing an atomic layer deposited zirconium silicon oxide film, and methods for forming such structures.

Claims (53)

1. A method comprising:

forming a dielectric layer containing a zirconium silicon oxide film in an integrated circuit, the zirconium silicon oxide film formed by atomic layer deposition including:

pulsing a zirconium precursor containing silicon; and

pulsing a silicon precursor, the silicon precursor being different from the zirconium precursor.

2. The method of claim 1 , wherein pulsing a silicon precursor includes pulsing a silicon precursor to adjust the silicon content in the zirconium silicon oxide film.

3. The method of claim 1 , wherein pulsing a zirconium precursor containing silicon includes pulsing a dichlorobis[bis(trimethylsilyl)amido]zirconium precursor.

4. The method of claim 1 , wherein pulsing a silicon precursor includes pulsing a silicon halide precursor.

5. A method comprising:

forming a dielectric layer containing a zirconium silicon oxide film in an integrated circuit, the zirconium silicon oxide film formed by atomic layer deposition using a dichlorobis[bis(trimethylsilyl)amido]zirconium precursor, an oxidant reactant precursor to the dichlorobis[bis(trimethylsilyl)amido]zirconium precursor, and a silicon halide precursor.

6. The method of claim 5 , wherein the method includes controlling the use of the silicon halide precursor to adjust the silicon content in the zirconium oxide film to adjust for silicon deposited using the dichlorobis[bis(trimethylsilyl)amido]zirconium precursor.

7. The method of claim 5 , wherein using a silicon halide precursor includes using SiCl 4 as a precursor.

8. The method of claim 5 , wherein using an oxidant reactant precursor to the dichlorobis[bis(trimethylsilyl)amido]zirconium precursor includes using water vapor.

9. The method of claim 5 , wherein forming a dielectric layer containing a zirconium silicon oxide film includes forming an amorphous ZrSi x O y film.

10. The method of claim 5 , wherein forming a dielectric layer containing a zirconium silicon oxide film includes forming the dielectric layer substantially as the zirconium silicon oxide film.

11. The method of claim 5 , wherein forming the dielectric layer includes forming the dielectric layer as a dielectric in a capacitor in the integrated circuit.

12. The method of claim 5 , wherein forming the dielectric layer includes forming the dielectric layer as a dielectric in a capacitor of a dynamic random access memory in the integrated circuit.

13. The method of claim 5 , wherein forming the dielectric layer includes forming the dielectric layer as a gate insulator in a silicon complementary metal oxide semiconductor transistor.

14. The method of claim 5 , wherein forming the dielectric layer includes forming the dielectric layer as a tunnel gate insulator in a flash memory device.

15. The method of claim 5 , wherein forming the dielectric layer includes forming the dielectric layer as an inter-gate insulator in a flash memory device.

16. The method of claim 5 , wherein forming the dielectric layer includes forming the dielectric layer as a dielectric in a NROM flash memory.

17. The method of claim 5 , wherein forming the dielectric layer as a dielectric in a NROM flash memory includes forming the dielectric layer as a nanolaminate.

18. A method comprising:

depositing a layer including ZrO x by atomic layer deposition on a substrate using a dichlorobis[bis(trimethylsilyl)amido]zirconium precursor and an oxidant reactant precursor to the dichlorobis[bis(trimethylsilyl)amido]zirconium precursor; and

depositing a layer of SiO y by atomic layer deposition on the substrate using a silicon halide precursor to form a zirconium silicon oxide film in an integrated circuit.

19. The method of claim 18 , wherein an oxidant reactant precursor to the dichlorobis[bis(trimethylsilyl)amido]zirconium precursor includes using a H 2 O precursor.

20. The method of claim 18 , wherein using a silicon halide precursor includes using SiCl 4 .

21. The method of claim 18 , wherein forming a dielectric layer containing a zirconium silicon oxide film includes forming an amorphous ZrSi x O y film.

22. The method of claim 18 , wherein forming a dielectric layer containing a zirconium silicon oxide film includes forming the dielectric layer substantially as a zirconium silicon oxide.

23. The method of claim 18 , wherein the method further includes forming the zirconium silicon oxide film with a predetermined amount of silicon with respect to the total amount of silicon and zirconium in the zirconium silicon oxide film.

24. The method of claim 18 , wherein depositing a layer substantially of ZrO x by atomic layer deposition and depositing a layer of SiO y by atomic layer deposition includes depositing an atomic layer substantially of ZrO x followed by depositing an atomic layer of SiO y.

25. A method comprising:

forming a memory array in an integrated circuit including forming a dielectric layer in a cell of the memory array, wherein forming the dielectric layer includes forming a zirconium silicon oxide film by atomic layer deposition using a dichlorobis[bis(trimethylsilyl)amido]zirconium precursor, an oxidant reactant precursor to the dichlorobis[bis(trimethylsilyl)amido]zirconium precursor, and a silicon halide precursor.

26. The method of claim 25 , wherein using a silicon halide precursor includes using SiCl 4 .

27. The method of claim 25 , wherein forming the dielectric layer includes forming the dielectric layer substantially as ZrSi x O y .

28. The method of claim 25 , wherein the method further includes forming the zirconium silicon oxide film with a predetermined amount of silicon with respect to the total amount of silicon and zirconium in the zirconium silicon oxide film.

29. The method of claim 25 , wherein forming a zirconium silicon oxide film by atomic layer deposition includes depositing an atomic layer of ZrO x followed by depositing an atomic layer of SiO y .

30. The method of claim 25 , wherein forming a memory array includes forming a memory array of a dynamic random access memory.

31. The method of claim 25 , wherein forming the dielectric layer includes forming the dielectric layer as a dielectric in a capacitor of a dynamic random access memory.

32. The method of claim 25 , wherein forming the dielectric layer includes forming the dielectric layer as a gate insulator in a silicon complementary metal oxide semiconductor transistor.

33. The method of claim 25 , wherein forming the dielectric layer includes forming the dielectric layer as a tunnel gate insulator in a flash memory device.

34. The method of claim 25 , wherein forming the dielectric layer includes forming the dielectric layer as an inter-gate insulator in a flash memory device.

35. The method of claim 25 , wherein forming the dielectric layer includes forming the dielectric layer as a dielectric in a NROM flash memory.

36. A method comprising:

providing a controller;

coupling an integrated circuit to the controller, wherein at least one of the controller or the integrated circuit includes a dielectric layer containing a zirconium silicon oxide film formed by atomic layer deposition using a dichlorobis[bis(trimethylsilyl)amido]zirconium precursor, an oxidant reactant precursor to the dichiorobis [bis(trimethylsilyl)amido]zirconium precursor, and a silicon halide precursor.

37. The method of claim 36 , wherein using a silicon halide precursor includes using SiCl 4 as a precursor.

38. The method of claim 36 , wherein coupling an integrated circuit to the controller includes coupling a memory device formed as the integrated circuit, the memory device having the dielectric layer containing the zirconium silicon oxide film.

39. The method of claim 36 , wherein providing a controller includes providing a processor.

40. The method of claim 36 , wherein coupling an integrated circuit to the controller includes coupling a mixed signal integrated circuit formed as the integrated circuit having the dielectric layer containing the zirconium silicon oxide film.

41. The method of claim 36 , wherein a zirconium silicon oxide film formed by atomic layer deposition includes the zirconium silicon oxide film formed substantially as an amorphous ZrSi x O y film.

42. The method of claim 36 , wherein a zirconium silicon oxide film formed by atomic layer deposition includes the zirconium silicon oxide film formed with a predetermined amount of silicon with respect to the total amount of silicon and zirconium in the zirconium silicon oxide film.

43. The method of claim 36 , wherein a zirconium silicon oxide film formed by atomic layer deposition includes the zirconium silicon oxide film formed by depositing an atomic layer of ZrO x followed by depositing an atomic layer of SiO y .

44. The method of claim 36 , wherein the method is a method of forming an information handling system.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2005
From: AHN, KIE Y.; FORBES, LEONARD
To: MICRON TECHNOLOGY, INC.
Reel/Frame 016523/0131 →
Continuity (1)
Related Publication 20060244100A1 · Nov 2, 2006