IP Library Granted Patent US 7,405,137
Granted Patent B2
US 7,405,137 · App. 11/157,855 · Granted Jul 29, 2008

Method of dicing a semiconductor substrate into a plurality of semiconductor chips by forming two cutting grooves on one substrate surface and forming one cutting groove on an opposite substrate surface that overlaps the two cutting grooves

Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 7,405,137
App. No.
11/157,855
Granted
Jul 29, 2008
Kind
B2
Abstract

In a manufacturing method of a semiconductor device, a semiconductor substrate having a plurality of semiconductor chips formed on one of principal surfaces of the substrate is cut into the plurality of semiconductor chips through dicing. A first cutting process is formed on one of the principal surfaces of the substrate to produce two cutting grooves between two neighboring ones of the plurality of semiconductor chips, each cutting groove being adjacent to one of the neighboring ones of the plurality of semiconductor chips. A second cutting process is performed on the other of the principal surfaces of the substrate to produce a cutting groove overlapping the two cutting grooves produced by the first cutting process.

Claims (17)

1. A manufacturing method of a semiconductor device in which a semiconductor substrate having a plurality of semiconductor chips formed on one of principal surfaces of the substrate is cut into the plurality of semiconductor chips through dicing, comprising the steps of:

performing a first cutting process on one of the principal surfaces of the substrate to produce two cutting grooves between two neighbouring ones of the plurality of semiconductor chips, each cutting groove being adjacent to one of the neighbouring ones of the plurality of semiconductor chips; and

performing a second cutting process on the other of the principal surfaces of the substrate to produce a cutting groove overlapping the two cutting grooves produced by the first cutting process.

2. The manufacturing method of claim 1 wherein a step cut method is used in the first cutting process.

3. The manufacturing method of claim 1 wherein a dicing blade having a width larger than a width of a scribe line is used in the second cutting process.

4. The manufacturing method of claim 1 wherein the cutting grooves formed in the substrate by the first cutting process have a depth smaller than a depth of the cutting groove formed in the substrate by the second cutting process.

5. The manufacturing method of claim 1 wherein the cutting grooves formed in the substrate by the first cutting process have side surfaces with a positive taper toward a depth direction from the one of the principal surfaces of the substrate.

6. The manufacturing method of claim 1 wherein projection electrodes are formed on each of the plurality of semiconductor chips on the one of the principal surfaces of the substrate.

7. The manufacturing method of claim 1 further comprising the steps of:

attaching a first dicing tape to the other of the principal surfaces of the substrate before the first cutting process; and

attaching, after the first cutting process and before the second cutting process, a second dicing tape to the one of the principal surfaces of the substrate and removing the first dicing tape from the other of the principal surfaces of the substrate, wherein the second dicing tape has a flexible layer.

8. The manufacturing method of claim 1 wherein an outside edge of each of the dicing grooves formed in the substrate by the first dicing process is at a predetermined distance from a metal line in an outermost periphery of one of the plurality of semiconductor chips formed on the one of the principal surfaces of the substrate, and an outside edge of the dicing groove formed in the substrate by the second dicing process is located inside a position of the metal line.

9. The manufacturing method of claim 1 wherein a flat electrode layer is formed on each of the plurality of semiconductor chips formed on the one of the principal surfaces of the substrate.

10. The manufacturing method of claim 1 wherein each of the plurality of semiconductor chips produced by the second dicing process has a maximum width at a position near a center of a thickness of the semiconductor chip.

11. The manufacturing method of claim 1 further comprising the step of attaching, after the first cutting process and before the second cutting process, a dicing tape to the one of the principal surfaces of the substrate,

wherein the dicing tape is brought in contact with an intermediate part of the substrate between the dicing grooves formed in the substrate by the first dicing process.

12. The manufacturing method of claim 1 wherein, in the first dicing process, each of two dicing blades is positioned so that edges of the dicing blade are at a predetermined distance along a dicing line from a metal line located in an outermost periphery of each of the plurality of semiconductor chips formed on the one of the principal surfaces of the substrate.

Assignments (3)
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2005
From: TERAYAMA, SATOSHI; MATSUKI, HIROHISA
To: FUJITSU LIMITED
Reel/Frame 016716/0645 →
Priority Claims (1)
JP 2005-105233 · Mar 31, 2005 · national
Continuity (1)
Related Publication 20060223234A1 · Oct 5, 2006