IP Library › Granted Patent US 7,420,530
Granted Patent B2
US 7,420,530 · App. 11/416,120 · Granted Sep 2, 2008

Pixel circuit, display device method for controlling pixel circuit

Assignee: Sony Corporation
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Quick Facts
Patent No.
US 7,420,530
App. No.
11/416,120
Granted
Sep 2, 2008
Kind
B2
Abstract

A pixel electrode and a display device capable of lowering power consumption with a uniformity of luminance retained, and realizing a display image having a high contrast and a high image quality, wherein a correction period for correcting a variation in properties of a drive transistor in a pixel during a frame, a write period for driving a first switch by a first control line and writing a data signal from a signal line to the node, and a drive period for storing the written data signal and driving an electro-optical element, are set, and the drive is controlled so that an interval having the correction period, the write period, and the drive period, and an interval having the write period and the drive period without the correction period exist.

Claims (48)

1. A pixel circuit comprising:

an electro-optical element changing a luminance changes based on a flowing current,

a signal line supplied with a data signal corresponding to at least a luminance information;

a first control line;

a drive transistor forming a current supply line between a first terminal and a second terminal and controlling a current, flowing into the current supply line, based on a potential of a control terminal;

a node electrically couplable to the control terminal of the drive transistor; and

a first switch connected between the signal line and the node and controlled with a conductive state and a non-conducive state by the first control line, wherein

during a frame, the pixel circuit is able to set

a correction period for correcting a variation of property of the drive transistor in a pixel,

a write period for driving the first switch by the first control line and writing the data signal from the signal line to the node, and

a drive period for storing the written data signal and driving the electro-optical element, and

the pixel circuit is driven and controlled so that an interval having the correction period, the write period, and the drive period are carried out, and an interval having the write period and the drive period without the correction period exist.

2. A pixel circuit as set forth in claim 1 , wherein a coupling capacitance is connected between the node and the control terminal of the drive transistor, and

a voltage depending on a threshold voltage of the drive transistor is accumulated during the correction period at a both ends of the coupling capacitance.

3. A pixel circuit as set forth in claim 1 , wherein the correction period is set once per a plurality of a frame.

4. A pixel circuit as set forth in claim 1 , wherein the correction period is set once per a plurality of a field.

5. A pixel circuit as set forth in claim 1 , wherein an existence of the correction period is controlled in a plurality of row units.

6. A pixel circuit as set forth in claim 1 , wherein an existence of the correction period is controlled each in an odd numbered scan line unit and an even numbered scan line unit.

7. A pixel circuit as set forth in claim 1 , wherein an existence of the correction period is controlled in a plurality of column units.

8. A pixel circuit as set forth in claim 1 , wherein an existence of the correction period is controlled each in an odd numbered signal line unit and an even numbered signal line unit.

9. A pixel circuit as set forth in claim 1 , wherein an existence of the correction period is controlled in an adjoining pixel unit.

10. A display device comprising:

a plurality of a pixel circuit arranged in matrix;

a signal line interconnected in each column with respect to a matrix arrangement of the pixel circuit and supplied with a data signal corresponding to at least a luminance information;

a first control line interconnected in each row with respect to a matrix arrangement of the pixel circuit; and

a drive unit,

the pixel circuit including

an electro-optical element changing a luminance based on a flowing current,

a signal line supplied with the data signal corresponding to at least the luminance information,

a drive transistor forming a current supply line between a first terminal and a second terminal and controlling a current, flowing into the current supply line, based on a potential of a control terminal,

a node electrically couplable to the control terminal of the drive transistor, and

a first switch connected between the signal line and the node and controlled with a conductive state and a non-conductive state by the first control line, wherein

during a frame, the drive unit is able to set

a correction period for correcting a variation of property of the drive transistor in a pixel,

a write period for driving the first switch by the first control line and writing the data signal from the signal line to the node, and

a drive period for storing the written data signal and driving the electro-optical element, and

the drive unit drives and controls so that an interval having the correction period, the write period, and the drive period are carried out, and an interval having the write period and the drive period without the correction period exist.

11. A display device as set forth in claim 10 , wherein a coupling capacitance is connected between the node and the control terminal of the drive transistor, and

a voltage depending on a threshold voltage of the drive transistor is charged during the correction period at a both ends of the coupling capacitance.

12. A method for controlling a pixel circuit, having an electro-optical element changing a luminance based on a flowing current, a signal line supplied with a data signal corresponding to at least a luminance information, a first control line, a drive transistor forming a current supply line between a first terminal and a second terminal and controlling a current, flowing into the current supply line, based on a potential of a control terminal, a node capable of electrically coupling the control terminal of the drive transistor, and a first switch connected between the signal line and the node and controlled with a conductive state and a non-conductive state by the first control line, the method comprising the step of:

controlling the pixel circuit so that a correction period for correcting, a variation of property of the drive transistor in a pixel, a write period for driving the first switch by the first control line and writing the data signal from the signal line to the node, and a drive period for storing the written data signal and driving the electro-optical element are set during a frame, and an interval having the correction period, the write period, and the drive period, and an interval having the write period and the drive period without the correction period exist.

13. A method for controlling a pixel circuit as set forth in claim 12 , wherein the correction period is set once per a plurality of the frame.

14. A method for controlling a pixel circuit as set forth in claim 12 , wherein the correction period is set once per a plurality of a field.

15. A method for controlling a pixel circuit as set forth in claim 12 , wherein an existence of the correction period is controlled in a plurality of row units.

16. A method for controlling a pixel circuit as set forth in claim 12 , wherein an existence of the correction period is controlled each in an odd numbered scan line unit and an even numbered scan line unit.

17. A method for controlling a pixel circuit as set forth in claim 12 , wherein an existence of the correction period is controlled in a plurality of column units.

18. A method for controlling a pixel circuit as set forth in claim 12 , wherein an existence of the correction period is controlled each in an odd numbered signal line unit and an even numbered signal line unit.

19. A method for controlling a pixel circuit as set forth in claim 12 , wherein an existence of the correction period is controlled in an adjoining pixel unit.

Assignments (3)
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2006
From: ASANO, MITSURU; YUMOTO, AKIRA; FUJIMURA, HIROSHI
To: SONY CORPORATION
Reel/Frame 017864/0705 →
Priority Claims (1)
JP 2005-139898 · May 12, 2005 · national
Continuity (1)
Related Publication 20060256058A1 · Nov 16, 2006