IP Library › Granted Patent US 7,473,644
Granted Patent B2
US 7,473,644 · App. 10/883,215 · Granted Jan 6, 2009

Method for forming controlled geometry hardmasks including subresolution elements

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,473,644
App. No.
10/883,215
Granted
Jan 6, 2009
Kind
B2
Abstract

Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of precise subresolution features useful for forming integrated circuits. The resulting symmetrical hardmask spacers with their symmetric upper portions may be used to accurately etch well-defined, high aspect ratio features in the underlying substrate. Some disclosed methods also enable simultaneous formation of hardmask structures of various dimensions, of both conventional and subresolution size, to enable etching structural features of different sizes in the underlying substrate.

Claims (70)

1. A method for forming hardmask elements on a substrate comprising:

forming a first material layer on a substrate;

forming a second material layer on the first material layer;

forming a plurality of laterally-spaced, discrete structures comprising the first and second material layers on the substrate and leaving intervening portions of the substrate exposed, the plurality of laterally-spaced, discrete structures each having a geometry defined by a top surface and substantially vertical sidewalls;

depositing a hardmask material layer over the top surfaces and sidewalls of the plurality of laterally-spaced, discrete structures and the intervening, exposed portions of the substrate;

removing portions of the hardmask material layer over the top surfaces of the laterally-spaced, discrete structures and the intervening portions of the substrate while leaving spacers of the hardmask material layer on the sidewalls of the laterally-spaced, discrete structures;

planarizing the plurality of laterally-spaced, discrete structures to remove all of the second material layer and adjacent portions of the spacers; and

removing the first material layer to form a plurality of hardmask elements.

2. The method of claim 1 , further comprising defining at least one well within or at least one aperture through the substrate by etching using the hardmask elements to define boundaries thereof

3. The method of claim 1 , wherein the planarizing is effected by abrasive planarization.

4. The method of claim 3 , wherein the abrasive planarization comprises chemical mechanical planarization.

5. The method of claim 1 , further comprising selecting the substrate from a material comprising a layer of semiconductor material and a layer of glass material.

6. The method of claim 1 , further comprising forming the first material layer from silicon nitride.

7. The method of claim 1 , further comprising forming the first material layer to a thickness of about 500 Å.

8. The method of claim 1 , further comprising forming the second material layer from silicon dioxide.

9. The method of claim 1 , further comprising forming the second material layer to a thickness of about 500 Å.

10. The method of claim 1 , further comprising forming the hardmask material layer from a material selected from the group consisting of silicon dioxide, silicon nitride, polysilicon. titanium nitride, amorphous carbon, and aluminum oxide.

11. The method of claim 1 , further comprising forming the hardmask material layer to a thickness of about 300 Å.

12. The method of claim 1 , further comprising planarizing the spacers to a height of about 2000 Å.

13. The method of claim 1 , wherein forming the plurality of laterally-spaced, discrete structures is effected by selectively masking portions of the second material layer and etching.

14. The method of claim 1 , wherein removing the portions of the hardmask material layer is effected by etching.

15. A method for forming hardmask elements of different sizes on a substrate comprising:

forming a first material layer on a substrate;

forming a second material layer on the first material layer;

forming a plurality of laterally-spaced, discrete structures comprising the first and second material layers on the substrate and leaving intervening portions of the substrate exposed, the plurality of laterally-spaced, discrete structures each having a geometry defined by a top surface and substantially vertical sidewalls;

depositing a hardmask material layer over the top surfaces and sidewalls of the plurality of laterally-spaced, discrete structures and the intervening, exposed portions of the substrate;

removing portions of the hardmask material layer over the top surfaces of the laterally-spaced, discrete structures and the intervening portions of the substrate while leaving spacers of the hardmask material layer on the sidewalls of the laterally-spaced, discrete structures;

planarizing the plurality of laterally-spaced, discrete structures to remove all of the second material layer and adjacent portions of the spacers;

protecting the top surface of at least one of the plurality of laterally-spaced, discrete structures; and

removing the first material layer of any unprotected laterally-spaced, discrete structure to form a plurality of hardmask elements having a first lateral dimension and at least one hardmask element having a second, larger dimension.

16. The method of claim 15 , further comprising defining at least one well within or at least one aperture through the substrate by etching using the hardmask elements to define boundaries thereof.

17. The method of claim 15 , wherein the planarizing is effected by abrasive planarization.

18. The method of claim 17 , wherein the abrasive planarization comprises chemical mechanical planarization.

19. The method of claim 15 , further comprising selecting the substrate from a material comprising a layer of semiconductor material and a layer of glass material.

20. The method of claim 15 , further comprising forming the first material layer from silicon nitride.

21. The method of claim 15 , further comprising forming the first material layer to a thickness of about 500 Å.

22. The method of claim 15 , further comprising forming the second material layer from silicon dioxide.

23. The method of claim 15 , further comprising forming the second material layer to a thickness of about 500 Å.

24. The method of claim 15 , further comprising forming the hardmask material layer from a material selected from the group consisting of silicon dioxide, silicon nitride, polysilicon, titanium nitride, amorphous carbon, and aluminum oxide.

25. The method of claim 15 , further comprising forming the hardmask material layer to a thickness of about 300 Å.

26. The method of claim 15 , further comprising planarizing the spacers to a height of about 2000 Å.

27. The method of claim 15 , wherein forming the plurality of laterally-spaced, discrete structures is effected by selectively masking portions of the second material layer followed by etching.

28. The method of claim 15 , wherein removing the portions of the hardmask material layer is effected by etching.

29. The method of claim 15 , further comprising protecting the top surface of the at least one of the plurality of laterally-spaced, discrete structures by applying a resist thereto.

30. A method for forming hardmasks of different sizes on a substrate comprising:

forming a first material layer on a substrate;

forming a second material layer on the first material layer;

forming a third material layer on the second material layer;

forming a plurality of discrete structures comprising the first, second and third material layers on the substrate, the plurality of discrete structures each having a geometry defined by a top surface and substantially vertical sidewalls;

protecting the top surface of at least one of the discrete structures;

depositing a hardmask material layer over the top surfaces and sidewalls of the plurality of discrete structures and intervening portions of the substrate;

removing portions of the hardmask material layer over the top surfaces of the discrete structures and intervening portions of the substrate and removing the third material layer and a portion of the second material layer of any discrete structure having an unprotected top surface while leaving spacers of the hardmask material layer on the sidewalls of the discrete structures;

planarizing the plurality of discrete structures to remove all of the second material layer and adjacent portions of the spacers of any discrete structure having an unprotected top surface; and

removing the first material layer of any discrete structure having an unprotected top surface to form a plurality of hardmask elements having a first lateral dimension and at least one hardmask element having a second larger lateral dimension.

31. The method of claim 30 , further comprising defining at least one well within or at least one aperture through the substrate by etching using the hardmask elements to define boundaries thereof.

32. The method of claim 30 , wherein the planarizing is effected by abrasive planarization.

33. The method of claim 32 , wherein the abrasive planarization comprises chemical mechanical planarization.

34. The method of claim 30 , further comprising selecting the substrate from a material comprising a layer of semiconductor material and a layer of glass material.

35. The method of claim 30 , further comprising forming the first material layer from silicon nitride.

36. The method of claim 30 , further comprising forming the first material layer to a thickness of about 500 Å.

37. The method of claim 30 , further comprising forming the second material layer from silicon dioxide.

38. The method of claim 30 , further comprising forming the second material layer to a thickness of about 500 Å.

39. The method of claim 30 , further comprising forming the hardmask material layer from a material selected from the group consisting of silicon dioxide, silicon nitride, polysilicon, titanium nitride, amorphous carbon, and aluminum oxide.

40. The method of claim 30 , further comprising forming the hardmask material layer to a thickness of about 300 Å.

41. The method of claim 30 , further comprising planarizing the spacers of any unprotected discrete structure to a height of about 2000 Å.

42. The method of claim 30 , wherein forming the plurality of discrete structures is effected by selectively masking portions of the third material layer and etching.

43. The method of claim 30 , wherein removing portions of the hardmask material layer over the top surfaces of the discrete structures and intervening portions of the substrate and removing the third material layer and a portion of the second material layer of any discrete structure having an unprotected top surface is effected by etching.

44. The method of claim 30 , further comprising protecting the top surface of the at least one of the plurality of discrete structures by applying a resist thereto.

45. The method of claim 30 , further comprising forming the third material layer to a thickness of about 100 Å.

46. The method of claim 30 , further comprising forming the third material layer from aluminum oxide.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2004
From: LANE, RICHARD H.; FISHBURN, FRED
To: MICRON TECHNOLOGY, INC.
Reel/Frame 015553/0459 →
Continuity (1)
Related Publication 20060003182A1 · Jan 5, 2006