Method for forming robust solder interconnect structures by reducing effects of seed layer underetching
View Patent ↗A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.
1. An interconnect structure for a semiconductor device, comprising:
a via defined in a passivation layer so as expose a top metal layer in the semiconductor device;
a seed layer formed over said passivation layer, sidewalls of said via, and said top metal layer;
a barrier layer formed over an exposed portion of said seed layer, said exposed portion defined by a first patterned opening of a first diameter; and
a solder material formed over said barrier layer using a second patterned opening of a second diameter;
wherein said second patterned opening is configured such that said second diameter is larger than said first diameter.
2. The interconnect structure of claim 1 , wherein exposed portions of said seed layer are removed so as to define a ball limiting metallurgy (BLM) such that portions of said seed layer do not undercut said barrier layer.
3. The interconnect structure of claim 1 , wherein:
said seed layer comprises a titanium-tungsten/chrome-copper/copper (TiW/CrCu/Cu) layer; and
said barrier layer comprises a nickel/copper layer.
4. The interconnect structure of claim 3 , wherein said second diameter exceeds said first diameter by about 20 to about 25 microns.
5. An interconnect structure for a semiconductor device, comprising:
a via defined in a passivation layer so as expose a top metal layer in the semiconductor device;
a seed layer formed over said passivation layer, sidewalls of said via, and said top metal layer;
a barrier layer formed over an exposed portion of said seed layer, said exposed portion defined by a first patterned opening;
said seed layer underneath said barrier having diffused regions including atoms from said barrier layer diffused therein through annealing so as to cause said diffused regions of said seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of said seed layer; and
a solder material formed over said barrier layer using a second patterned opening, wherein said second patterned opening is configured so as to have a larger diameter than said first patterned opening.
6. The interconnect structure of claim 5 , wherein said seed layer is etched, following annealing, so as to define a ball limiting metallurgy (BLM) such that remaining portions of said seed layer do not undercut said barrier layer.
7. The interconnect structure of claim 5 , further comprising a solder material formed over said barrier layer using said first patterned opening.
8. The interconnect structure of claim 5 , wherein atoms from said barrier layer are diffused into said seed layer by about one micron in x, y and z-directions.
9. The interconnect structure of claim 8 , wherein the electrical resistivity of said diffused regions of said seed layer exceed the electrical resistivity of said diffused regions of said seed layer by about one order of magnitude.
10. The interconnect structure of claim 5 , wherein:
said seed layer comprises a titanium-tungsten chrome-copper/copper (TiW/CrCu/Cu) layer; and
said barrier layer comprises a nickel/copper layer.