Packet processor memory interface with conflict detection and checkpoint repair
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. The packet processor implements a checkpoint repair mechanism allowing processing to restart from defined checkpoints. In some embodiments this is done with sub-sequence numbers. When a memory conflict is detected a restart signal is generated to backup and restart from a given checkpoint.
1. An apparatus for interfacing a packet processing engine with a memory system comprising:
a first data storage element storing information based upon a memory read comprising a first packet identifier and checkpoint information;
a second data storage element storing information based upon a memory write comprising a second packet identifier;
write processing and conflict detection logic coupled to said first data storage element and said second data storage element, wherein said second data storage element is modified based on said memory write and said second data storage element is searched based on said memory read, and wherein a determination is made whether a memory conflict exists between said memory read and said memory write; and
logic for signaling a restart coupled to said write processing and conflict detection logic and utilizing said first associated packet identifier, wherein said restart signal utilizes said checkpoint information.
2. The apparatus of claim 1 further comprising:
read processing logic coupled to said first data storage element and said second data storage element, wherein said first data storage element is modified based on said memory read and said second data storage element is searched based on said memory read.
3. The apparatus of claim 1 wherein:
said first data storage element comprises a plurality of entries each comprising a packet identifier, checkpoint information and an address;
said second data storage element comprises a plurality of entries each comprising a packet identifier, write data and an address, wherein said memory write comprises an address and memory write data, and wherein said write processing and conflict detection logic stores said address, said second packet identifier and said memory write data into said second data storage element and searches said first data storage element for an entry with an address matching said address and a packet identifier greater than said second packet identifier.
4. The apparatus of claim 1 wherein said first packet identifier and said second packet identifier are sequence numbers that indicate the order of arrival of packets at said packet processing engine.
5. The apparatus of claim 1 wherein said packet processing engine is a multithreaded processor that processes multiple packets in parallel.
6. The apparatus of claim 1 wherein said packet processing engine is a multiprocessor that processes multiple packets in parallel.
7. A method of interfacing a packet processor with a memory system comprising:
receiving a memory read comprising a first packet identifier and checkpoint information from a packet processing engine;
storing information based upon said memory read into a first data storage element;
returning speculative read data to the packet processing engine responsive to said memory read;
receiving a memory write comprising a second packet identifier from said packet processing engine;
storing information based on said memory write into said second data storage element;
searching said first data storage element using information based on said memory write;
determining if said speculative read data is incorrect; and
restarting processing of said packet associated with said speculative read data if said speculative read data is incorrect, wherein said restarting uses said checkpoint information to allow restarting packet processing at a checkpoint established by said packet processor.
8. The method of claim 7 wherein returning speculative read data comprises:
searching a second data storage element using information based on said memory read;
responsive to said searching detecting a match, retrieving data from said second storage element; and
responsive to said searching not detecting a match, retrieving data from said memory system.
9. The method of claim 7 wherein:
said memory read comprises a first memory address;
said storing information comprises storing at least a portion of said first memory address and said first packet identifier in a read table; and
said searching comprises searching a write table for an entry with an address matching at least a portion of said first memory address and a packet identifier equal to or less than said first packet identifier.
10. The method of claim 7 wherein
said memory write comprises a second memory address and memory write data;
said storing information based on said memory write comprises storing said second memory address, said second packet identifier and said memory write data in a write table; and
said searching said first data storage comprises searching a read table for an entry with an address matching at least a portion of said second memory address and a packet identifier greater than said second packet identifier.
11. The method of claim 7 wherein said first packet identifier and said second packet identifier are sequence numbers that indicate the order of arrival of packets at said packet processing engine.
12. The method of claim 7 wherein said packet processing engine is a multithreaded processor that processes multiple packets in parallel.
13. The method of claim 7 wherein said packet processing engine is a multiprocessor that processes multiple packets in parallel.